Jobs / United States / Intel Corporation
Pre-Silicon Verification Engineer
Intel Corporation · 🇺🇸 6 Locations
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Intel Corporation paid sponsored hires in similar roles287 certified filings for “Process Engineer” (Materials Engineers) in OR: $113k–$133k, median $133k. Most were filed at wage level III (87%) — 3 lottery entries, ≈46% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Intel Corporation
The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Intel Corporation →
About the role
Job Details: Job Description: About Intel's Central Engineering Group Intel's Central Engineering Group (CEG) focuses on enhancing engineering execution and expanding market opportunities through internal product development and external ASIC design services. Guided by a data-driven approach, CEG drives scalable, impactful solutions across Intel's engineering processes while maintaining a commitment to delivering high-quality results. Join a team dedicated to revolutionizing engineering methodologies and supporting Intel's industry leadership. Position Overview As an IP Design Verification Engineer, you will play a crucial role in ensuring the functional accuracy and reliability of clock generator IPs, such as PLL and FLL, within Intel's innovative product development lifecycle. You will actively develop verification environments, implement tests, and debug pre-silicon issues to meet rigorous specification requirements. Your contributions will directly impact the seamless integration of IPs into Intel's cutting-edge designs and ensure the highest standards of quality and performance. Key Responsibilities • Develop test benches, verification environments, and tests using System Verilog and UVM to ensure comprehensive IP validation • Perform functional verification for clock generator IPs such as PLL and FLL, ensuring conformance to microarchitecture specifications • Maintain and refine verification infrastructure and methodologies for multiple IP generations • Debug and root-cause pre-silicon issues within the verification environment • Document test plans and participate in technical reviews with design teams • Collaborate cross-functionally with architects, RTL developers, and analog design teams to enhance verification of architectural and microarchitectural features • Lead Mixed Signal Validation activities, including AMS simulations, schematic debugging, and resolving cross-functional issues • Contribute to the definition and refinement of architectural and microarchitectural features for IP design What We're Looking For To be successful in this role, you should demonstrate the following professional traits: • A collaborative mindset with the ability to work effectively across cross-functional teams including architects, RTL developers, and analog design teams • Strong attention to detail when documenting test plans, debugging pre-silicon issues, and ensuring conformance to specification requirements • A proactive approach to problem-solving, with the ability to root-cause complex technical issues and drive them to resolution Qualifications: Minimum Qualifications Bachelor's Degree in Electrical or Computer Engineering or a related field, with 4+ years of relevant experience; OR Master's Degree in Electrical or Computer Engineering or a related field, with 3+ years of relevant experience; OR PhD in Electrical or Computer Engineering or a related field, with 1+ years of relevant experience 2+ years of experience in/with: • Design verification and validation methodologies, including UVM, System Verilog, and industry-standard EDA tools • Scripting languages such as Python and Perl Preferred Qualifications • Expertise in System Verilog UVM coding and debugging • Familiarity with PLL/FLL or SOC clocking and related RTL development Join Intel's Central Engineering Group today, where your skills will drive innovation, quality, and engineering excellence while advancing Intel's industry-leading technology solutions. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Texas, Austin Posting Statement: All qualif