Senior Lead AI Systems and Performance Architect – LLM Inference

Start free →

Or apply yourself on the official page →

About the role

Job Details: Job Description: About the Role and Team The Intel DCG AISOC organization is developing the future of high-performance accelerated AI platforms. Real-world inference performance, latency SLOs, and TCO are governed by full-system interplay: dynamic batching, distributed KV cache movement, scale-up fabrics, and heterogeneous host-accelerator memory hierarchies. We are seeking a hands-on, technically deep Senior Lead AI Systems and Performance Architect to drive the technical direction, development, and system-level analysis of our End-to-End LLM Inference Simulation Platform. In this role, you will lead the technical execution of the simulation platform, define modeling workflows, and conduct dynamic trace replays. Your mission is to identify full-system bottlenecks, quantify GPU optimization, evaluate host CPU offloading, size memory subsystems, and assess high-speed interconnects -translating simulation findings into actionable engineering insights to guide Intel's future AI inference SoC and platform architectures. ________________________________________ Key Responsibilities: 1. Simulation Platform and Workflow Leadership • Technical Ownership: Lead the technical direction and continuous evolution of a discrete-event simulation platform modeling distributed multi-accelerator inference systems. • Serving Stack Modeling: Model critical serving mechanisms: e.g.continuous batching, chunked prefill, prefill-decode disaggregation, and dynamic KV cache allocation. • Fabric and Pipeline Abstraction: Integrate behavioral models for scale-up interconnects (UALink, PCIe Gen 6/7), capturing latency, arbitration, and collective communications (All-to-All, All-Reduce). • Workflow Automation: Design automated simulation pipelines to ingest empirical accelerator performance tables, execute parameter sweeps, and analyze results. 2. Dynamic Trace Replay and Bottleneck Analysis • Production Trace Replay: Drive the ingestion and replay of realistic production traces, capturing arrival burstiness, diverse prompt/output distributions, and shared prefix contexts. • Agentic Workload Modeling: Keep the simulator aligned with emerging patterns, specifically Agentic workflows (multi-step tool calls, state branches) and long-context KV cache demands. • Root-Cause Isolation: Conduct sensitivity analyses to isolate bottlenecks across compute throughput, memory bandwidth, bus latency, scale-up fabric contention, or scheduling overheads. • Metric Evaluation: Evaluate trade-offs across SLOs (TTFT, TPOT, ITL, queue wait times) against cluster throughput, power, and cost. 3. HW/SW Co-Design and Platform Recommendations • Silicon Architecture Input: Translate findings into architectural proposals for the AI SoC team, defining balanced compute-to-memory ratios, SRAM sizes, and interface configurations. • Platform Optimization: Evaluate the host CPU's role in the inference pipeline to identify offloading opportunities (orchestration, tokenization, routing, tiered KV cache staging). • Memory Hierarchy Sizing: Provide workload-grounded capacity and bandwidth recommendations, evaluating HBM/LPDDR vs. tiered system memory. 4. Team Leadership and Collaboration • Mentorship and Quality: Guide team members on simulation methodologies, code quality, model calibration, and experimental rigor. • Cross-Team Alignment: Partner with silicon architects, software engineers, and platform teams to translate architectural questions into structured simulation studies. Qualifications: Qualifications: Minimum Qualifications: • Education: Ph.D. or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related quantitative field. • Experience: Ph.D. with 4-6+ years (or Master's with 6-8+ years, or Bachelor's with 8-10+ years) in system perfo

View the official posting →