Principal ASIC Design Engineer

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About the role

Principal ASIC Design Engineer    This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Job Family Definition: Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication. Management Level Definition: Contributions have visible technical impact on a product or major subcomponent.  Applies in-depth professional knowledge and innovative ideas to solve complex problems. Visible contributions improve time-to-market, achieve cost reductions, or satisfy current and future unmet customer needs. Recognized internal authority on key technology area applying innovative principles and ideas. Provides technical leadership for significant project/program work. Leads or participates in cross-functional initiatives and contributes to mentorship and knowledge sharing across the organization. Responsibilities:   • Architect complex modules and subsystems used in high performance networking chips.   • Write detailed   functional   as well as the micro-architecture specification for your   module with   that   meet the power/area/performance targets.   • Implement the design using Verilog or System Verilog    • Write functional coverage/SVA to help verification catch corner case bugs.   • Make sure your module meets the power targets by using   state-of-the-art   power reduction techniques during architecture and implementation phases.   • Work with Physical design team for timing closure. Fix timing in RTL to meet the frequency target.    • Collaborate with the Verification team to make sure your block is fully   validated.   • Show leadership and provide guidance to new college-grad/junior   engineers and interns.    Recommended skills   • Bachelor’s degree in Electrical Engineering   required (Master’s   strongly   desired) with 15+ years of relevant experience.   • Strong analytical/ problem solving skills.   • Demonstrated skills in   leading and   implementing high performance   subsystems   from specification to final netlist.   • Knowledge of Computer Architecture/networking protocols through prior work is   strongly   desired.   • Strong coding skills in Verilog/System Verilog through   previous   work experience are necessary.    • Knowledge of synthesis/lint and other tools used in typical ASIC development   process   is highly desired.   • Excellent written and verbal communications skills   is   necessary.   • Knowledge of Perl/Python is strongly desired.    Accessibility HPE is committed to creati

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