Jobs / United States / Hewlett Packard Enterprise Company
Hardware Engineer 3
Hewlett Packard Enterprise Company · 🇺🇸 5 Locations
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 486 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 167 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Hewlett Packard Enterprise Company paid sponsored hires in similar roles2 certified filings for “Electrical/Hardware Engineer II” (Computer Hardware Engineers) in CA: $137k–$208k, median $172k. Most were filed at wage level IV (100%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Hewlett Packard Enterprise Company
The US Department of Labor certified 486 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 167 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Hewlett Packard Enterprise Company →
About the role
Hardware Engineer 3 This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: The Hardware Engineer will be a key contributor in the Hardware Sustaining group, you will be responsible for investigating and remediating critical hardware issues involving Juniper’s flag-ship networking products. You will document and share root cause findings and drive corrective actions. You will also drive hardware quality improvements into the next generation of Juniper products, based on lessons learned from these investigations. To be successful in this role, you will need the technical expertise to analyze and debug complex hardware products. You will require the ability to manage multiple priorities, and to drive issues to closure in a timely fashion. You will have to communicate and collaborate with multiple cross-functional teams to drive hardware quality goals. You will be a knowledge resource and an advocate for customer-focused hardware quality improvements in Juniper products. Responsibilities: • Lead failure analysis for critical hardware issues reported from field and factory. Determine and document root cause and corrective actions (RCCA). • Extract and share "Lessons Learned" from HW Sustaining failure analysis and share with appropriate Juniper teams to drive hardware quality improvement. • Collaborate with other Engineering and Manufacturing / Operations teams to drive corrective actions and hardware quality improvements. Work with Customer Support teams to understand and address customer hardware concerns. • Analyze hardware quality metrics and Repair Center findings to identify failure trends requiring investigation. • Provide technical leadership into multi-sourcing and change management activities on shipping products. • Review hardware test reports for new products prior to product release. Identify any quality concerns and work with the design teams to resolve. • Mentor and guide junior members, foster a collaborative environment, and encourage curiosity and knowledge sharing. Basic Requirements: • Bachelor’s degree or higher in Electrical, Electronics, or Computer Engineering • 8+ years of hardware design, debug and testing experience at the board and system level. • Expertise in debugging hardware problems using oscilloscopes, logic analyzers, and specialized networking test equipment such as IXIA/Spirent traffic analyzers, PCI analyzers, and in-circuit emulators • PCB design experience including schematic capture, PCB layout and routing. Familiarity with Cadence System Design tool suite. • Knowledge of networking hardware and associated components and interfaces such as switch ASICs, PHY, SerDes, CPU subsystems, optics, high-speed serial links, PoE, PCIe, NVMe, SATA, I2C, and USB. • Expertise in high speed circuit design and debug. Familiarity with signal and power integrity concepts and associated test and simulation tools. • Ability to manage multiple concurrent priorities and make progress. Able to manage hardware debug and desig