Senior Design Verification Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview As a Senior Design Verification Engineer, you will help build and validate complex connectivity silicon that enables the next generation of AI infrastructure. You will develop scalable verification environments, integrate UVM and C/C++ workflows, and partner closely with RTL designers to identify and resolve issues across simulation, co-simulation, and emulation. This is an opportunity to contribute across the verification lifecycle at a hyper-growth connectivity company. Your work will help deliver reliable, high-bandwidth products that connect CPUs, GPUs, memory, storage, and networking devices in rack-scale AI systems. Key Responsibilities • Verification Architecture and Planning • Build and maintain UVM-based verification environments using SystemVerilog and C/C++ integration through DPI/PLI. • Translate design specifications into verification plans, test strategies, and reusable test sequences. • Develop VIP abstraction layers that simplify and scale verification across projects and platforms. • Stimulus, Assertions, and Coverage • Create directed and constrained-random tests, transaction-level sequences, and user-controlled random constraints. • Write assertions and cover properties, analyze coverage data, and drive closure against verification goals. • Automate verification infrastructure and regression workflows using Python or Perl. • Debug and Cross-Functional Collaboration • Collaborate with RTL designers and other engineers to isolate, debug, and resolve failures across simulation, co-simulation, and FPGA-based emulation. • Apply third-party verification IP to validate protocols including PCIe, Ethernet, InfiniBand, DDR, NVMe , and USB. • Contribute to technical reviews, communicate verification status clearly, and manage priorities across multiple deliverables. Basic Qualifications • Bachelor’s degree in Electrical Engineering or a related field. • 2 - 5 years of experience developing or verifying complex SoC or silicon products. • Hands-on experience with SystemVerilog , UVM, and C/C++ in production verification environments. • Experience integrating C/C++ with SystemVerilog environments using DPI or PLI. • Experience developing verification infrastructure and tests in directed and constrained-random environments. • Strong debugging, prioritization, collaboration, and communication skills. • Authorized to work in Canada. Preferred Qualifications • Experience verifying PCIe across the physical, link, and transaction layers. • Experience with DDR4, DDR5, or HBM memory technologies. • Experience with FPGA-based verification or emulation. • Experience verifying Ethernet protocols across the PMA, PCS and MAC layers. • Experience debugging SoC software, including kernels, device drivers, or U-Boot. • Familiarity with verification IP from third-party vendors and protocol-level modeling. • Self-directed, adaptable approach with a strong focus on quality, execution, and customer impact. We know that creativity and