Jobs / United States / Astera Labs INC
Technical Chief of Staff for ASIC Engineering
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Summary We are seeking a technically strong Chief of Staff to the Head of Engineering who will also lead Engineering Program Management across Silicon Engineering. This role is a force-multiplier for Engineering leadership — driving org scale, decision velocity, and execution rigor. The ideal candidate brings deep technical fluency, structured problem-solving, and the ability to drive outcomes through influence rather than hierarchy. The role is fully in person in San Jose. Responsibilities — What You Will Own 1) Chief of Staff to Head of Engineering • Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs. • Frame and resolve high-leverage decisions — proactively surface blockers (technical, operational, organizational) before they escalate. • Manage escalations and organizational friction — diagnose root causes, coordinate resolution paths, and ensure durable fixes. • Partner cross-functionally with Hardware, Product, and Quality teams to ensure clarity of communication, alignment on priorities, and disciplined follow-through on decisions. • Support org design, headcount planning, and hiring prioritization for engineering teams. • Maintain alignment across functions through clear messaging and communication, validate exitance and validation of processes • Navigate org dynamics, build trust, and constructively challenge assumptions; maintain psychological safety. • Support the head of engineering with administrative and org related activities 2) Lead ASIC Tape out Management (Silicon Programs) • Status management — collect and track status across functions contributing to ASIC tapeouts. • Milestone tracking — maintain methodology checklists and boundary agreements to ensure schedule adherence. • IP and vendor tracking — own visibility into IP deliveries, version inventory, vendor issues, and escalation loops. • Quality & documentation — monitor quality KPIs, ensure engineering documentation completeness. • Requirements tracking — ensure PRDs/features are captured, tracked, baselined. • Resource monitoring — track compute, hardware, storage consumption and thresholds. • Internal reporting — generate status reporting for Silicon Engineering leadership. 3) Influence Without Authority • Drive cross-engineering outcomes through credibility, clarity, and follow-through — not hierarchy. • Create order in ambiguous spaces; shape scope where it is undefined. Qualifications • 10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies). • Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role. • Strong technical acumen — able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs. • Demonstrated experience running program cadence for complex s