Senior Engineer, Design Verification (MCU)

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About the role

• Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off • Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria • Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification • Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics • Apply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency • Drive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification • Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration • Review IP specifications and work with architects to translate requirements into robust verification plans and checkers • Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors • Work with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools • Mentor junior engineers and promote best‑in‑class verification practices and continuous improvement • Support Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required. • Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration. • Bachelor’s or Master’s degree in Electronics Engineering. • 2 - 4 years of experience in SoC Verification domains and working knowledge of industry-standard EDA toolkits. • Strong expertise in UVM-based testbench architecture and development. • Proven experience in metric-driven verification, including functional and code coverage closure. • Deep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices. • Experience with directed and constrained-random verification methodologies. • Experience debugging complex design issues in simulation, emulation, and post-silicon environments. • Proficiency in Verilog/SystemVerilog, with working knowledge of C/C++, and Shell scripting. • Experience in verification of MCU-based SoCs and subsystems, including CPU cores, AHB/APB/AXI bus protocols, interrupt controllers, GPIO, timers, UART, SPI, I2C, CAN, low-power features, and embedded peripherals. • Strong understanding of MCU architectures such as ARM Cortex-M, RISC-V, or equivalent embedded processor architectures. • Knowledge of firmware-driven verification techniques and embedded software interaction with MCU peripherals is desirable. • Strong analytical, problem-solving, and communication skills. Preferred/Plus Qualifications: Hands-on experience using AI/ML-based verification tools for: • Coverage gap analysis • Test stimulus optimization • Regression triage and coverage acceleration • Scripting expertise in Python, Perl, or TCL for automation and analytics. • Exposure to formal verification and hybrid formal-simulation flows. • Familiarity with high-speed or complex IPs, such as: • H.264 • Security, debug, or safety-critical IPs • Experience with MCU functional safety concepts (ISO 26262), low-power verification, secure boot, and embedded system validation is a plus. • Experience with firmware development/debugging in Embedded C or RTOS-based environments is desirable. Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is

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