Senior Staff Engineer – Analog/Mixed Signal Design

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About the role

We are seeking an experienced Senior Staff Engineer – Analog/Mixed-Signal Design with 10+ years of expertise in transistor-level analog IC design and a strong foundation in analog circuit design fundamentals. The ideal candidate has a proven track record of architecting, designing, integrating, and delivering complex analog IPs and mixed-signal subsystems from concept through production. Experience developing power management ICs is a plus. As part of Renesas' $2.6B Power Business Unit, you will help develop next-generation analog and mixed-signal solutions for multi-phase controllers and power management products that enable AI infrastructure and hyperscale computing platforms. Key Responsibilities • Architect, design, own, and deliver high-performance analog and mixed-signal IPs, including: • Source/sink LDOs • Positive and negative charge pumps • Relaxation and other oscillator architectures • Temperature sensors • Current-sense circuits • SAR ADCs • Protection circuits (UVLO, OVLO, OCP, thermal protection, etc.) • Core analog building blocks, including bandgap references, operational amplifiers, comparators, analog buffers, V-to-I converters, and high-speed level shifters • Drive innovative circuit architectures and design optimizations to meet challenging performance, power, area, yield, and reliability targets. • Lead analog IP development through the complete product lifecycle—from architecture and transistor-level implementation through silicon validation, production qualification, and manufacturing support. • Collaborate closely with layout engineers from floorplanning through chip-level integration, ensuring optimal analog layout, parasitic-aware design, and performance trade-offs. • Develop and optimize simulation methodologies across pre- and post-layout verification, balancing simulation accuracy, convergence, runtime, and debugging efficiency. • Establish and drive robust analog design methodologies, review processes, and quality checklists to maximize first-pass silicon success. • Define and review chip-level ESD, latch-up, and I/O protection strategies to ensure product robustness and reliability. • Mentor junior engineers and foster a culture of technical excellence across the team. • Lead or manage a small team of engineers, driving execution, mitigating technical risks, and delivering high-quality silicon on schedule. Minimum Qualifications • Bachelor's or Master's degree in Electrical Engineering or a related discipline. • 10+ years of hands-on experience in analog and mixed-signal IC design. • Demonstrated ownership of complex transistor-level analog IP from specification through silicon validation. • Strong understanding of: • Analog circuit design fundamentals • Semiconductor device physics and transistor-level design • Process corners, Monte Carlo analysis, mismatch, and noise • Extraction, post-layout simulation, and parasitic optimization • Analog layout techniques and layout-dependent effects (LDE) • ESD, latch-up, and chip-level reliability considerations • Proven experience across the complete IC development lifecycle, including architecture, design, verification, silicon bring-up, debugging, qualification, and production support. • Strong technical leadership, mentoring, communication, and cross-functional collaboration skills, with a passion for building high-performing engineering teams. Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is ou

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