Jobs / United States / Renesas Electronics America INC

Renesas Electronics America INC

Senior Analog Design Engineer

Chandler, Arizona, US Posted 18 days ago

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Sponsorship verdict

Sponsorship possible

One solid signal, not two. Worth applying, and worth asking about sponsorship early.

  • Employer is on a government sponsor recordThe US Department of Labor certified 56 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • What Renesas Electronics America INC paid sponsored hires in similar roles4 certified filings for “Staff Analog Engineer” (Electronics Engineers, Except Computer) in GA: $137k–$199k, median $161k.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
Employer is on a government sponsor record
The US Department of Labor certified 56 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
What Renesas Electronics America INC paid sponsored hires in similar roles
4 certified filings for “Staff Analog Engineer” (Electronics Engineers, Except Computer) in GA: $137k–$199k, median $161k. Most were filed at wage level IV (67%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

About the role

Renesas is seeking a Senior Analog Design Engineer to design and develop CMOS analog and mixed-signal circuits for advanced integrated circuits and power-management applications. In this role, you will own assigned analog blocks and subsystems from specification through design, verification, silicon characterization, and production. You will work independently on complex technical problems while collaborating with engineers across Analog Design, Digital Design, Verification, Layout, Applications, Test, and Product Engineering. This is an opportunity for an experienced analog IC designer to take meaningful ownership of silicon while continuing to expand technical depth in mixed-signal and power-management design. Relocation assistance is available for qualified candidates throughout the United States. Responsibilities • Design, simulate, and verify CMOS analog circuits and subsystems for mixed-signal and power-management ICs. • Translate product and system requirements into circuit-level specifications and practical design solutions. • Take ownership of assigned circuit blocks from specification through silicon validation and production release. • Design circuits such as amplifiers, comparators, oscillators, LDOs, voltage and current references, bias circuits, and related analog functions. • Evaluate circuit performance across process, voltage, and temperature conditions and identify technical risks. • Work closely with Layout Engineering to guide physical implementation and ensure layout quality and circuit performance. • Participate in block-, subsystem-, and chip-level design and verification reviews. • Perform silicon debugging, characterization, and laboratory evaluation of assigned designs. • Collaborate with Applications, Verification, Test, and Product Engineering to support qualification, test development, and production ramp. • Develop and maintain design specifications, simulation results, design-review materials, and technical documentation. • Apply sound engineering judgment to resolve complex technical problems and adapt established approaches where appropriate. • Share technical knowledge and provide guidance to less experienced engineers. • Hands-on experience in analog or mixed-signal integrated circuit design. • Strong CMOS transistor-level circuit design and simulation experience. • Experience designing analog circuit functions such as amplifiers, comparators, LDOs, oscillators, voltage references, current references, or bias circuits. • Strong proficiency with industry-standard EDA tools and the Cadence design environment. • Understanding of analog layout principles and the relationship between circuit design and physical implementation. • Experience with silicon characterization, debugging, or laboratory evaluation. • Strong analytical and problem-solving skills with the ability to independently resolve complex technical issues. • Ability to work effectively across multidisciplinary and geographically distributed engineering teams. • Strong written, verbal, presentation, and technical communication skills. Preferred Qualifications • Experience with PMIC or mixed-signal IC products. • Experience with DC/DC converters, power conversion, PLLs, filters, or other mixed-signal circuit functions. • Experience with analog mixed-signal or chip-level verification. • Experience supporting DFT, test development, qualification, or production ramp. Education & Experience • Bachelor’s degree in Electrical Engineering, Electronics Engineering, Microelectronics Engineering, or a related discipline with a minimum of 5 years of related experience; or • Master’s degree in a related engineering discipline with a minimum of 3 years of related experience; or • PhD in a related engineering discipline with

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