Jobs / United States / Tenstorrent USA INC
Datacenter & Agentic AI Workload Performance Analysis Engineer
Tenstorrent USA INC · 🇺🇸 Santa Clara, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 47 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Tenstorrent USA INC paid sponsored hires in similar roles13 certified filings for “Sr. Staff Engineer” (Computer Hardware Engineers) in CA: $177k–$230k, median $208k. Most were filed at wage level IV (58%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Tenstorrent USA INC
The US Department of Labor certified 47 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Tenstorrent USA INC →
About the role
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Workload Performance Analysis Engineer to help shape the performance of our next-generation RISC-V CPUs across modern datacenter and agentic AI workloads. In this role, you’ll sit at the intersection of hardware and software, bringing real-world applications onto RISC-V platforms, characterizing their behavior, and using workload analysis to uncover opportunities for better CPU performance, efficiency, and scalability. You’ll work closely with CPU architects, RTL designers, software engineers, and compiler teams to understand how demanding workloads exercise the CPU and translate those insights into architectural improvements. From reducing large production workloads for performance modeling to correlating simulation results with hardware behavior, your work will directly influence CPU architecture and performance across cloud, enterprise, and emerging AI workloads. This role is remote based out of North America. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are • You have a strong background in CPU performance analysis, workload characterization, or computer architecture, with experience connecting software behavior to hardware performance. • You understand modern CPU microarchitecture, including superscalar pipelines, speculative execution, memory hierarchies, and vector/SIMD architectures. • You enjoy digging into complex workloads, using profiling and simulation data to identify bottlenecks and turn analysis into actionable recommendations. • You’re comfortable working across hardware and software, from CPU microarchitecture and RTL to operating systems, compilers, runtimes, and applications. • You’re a strong technical communicator who enjoys collaborating with architects, designers, and software engineers on complex performance problems. What We Need • PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field, with strong research or industry experience in workload characterization, benchmark development, performance analysis, or simulation. • Deep understanding of CPU architecture and RISC-V, including pipelines, speculative execution, vector/SIMD extensions, memory hierarchies, and performance tradeoffs. • Hands-on experience with performance analysis and simulation tools such as Linux perf, strace, QEMU, or CPU microarchitecture simulators. • Strong programming skills in C/C++, Python, Bash/Shell, and assembly or intrinsic programming, with experience working close to the hardware/software boundary. • Strong understanding of systems software, including operating systems, virtualization, compilers, runtimes, and GNU/RISC-V software ecosystems. What You Will Learn • How real-world datacenter and agentic AI workloads influence CPU microarchitecture and architectural decisions. • How to connect workload characterization and performance modeling to CPU design, RTL implementation, emulation, and silicon. • How hardware/software co-des