Jobs / United States / Hewlett Packard Enterprise Company
Printed Circuit Board (PCB) Layout Engineer
Hewlett Packard Enterprise Company · 🇺🇸 2 Locations
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 486 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 167 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Hewlett Packard Enterprise Company paid sponsored hires in similar roles59 certified filings for “Systems/Software Engineer III” (Software Developers) in CA: $149k–$206k, median $183k. Most were filed at wage level II (43%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
Or apply yourself on the official page →
Sponsor Radar — Hewlett Packard Enterprise Company
The US Department of Labor certified 486 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 167 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Hewlett Packard Enterprise Company →
About the role
Printed Circuit Board (PCB) Layout Engineer This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: We are seeking an experienced Printed Circuit Board (PCB) Layout Engineer to design complex printed circuit boards (PCBs) for high-performance computing systems. The PCB Design Engineer will work independently to lay out and help release cutting-edge, high-speed PCBs into production. Responsibilities: • Design printed circuit board layouts using computer-aided design software, consistent with electrical engineering circuit-performance, signal-integrity, and EMI specifications; mechanical engineering form factor and thermal requirements; and manufacturing requirements. • Read and interpret schematics, system functionality and performance specifications, and company PCB design guidelines as necessary to complete printed circuit board layouts. • Determine PCB design approaches and parameters. • Influence design decisions related to the analysis and resolution of system-performance issues associated with printed circuit board layout. Education and Experience: • Associate degree or equivalent technical degree with 10+ years of experience laying out complex, multilayer, high-speed printed circuit boards. • Bachelor’s degree in Electrical Engineering or equivalent technical degree with 4+ years of experience laying out complex, multilayer, high-speed printed circuit boards. • Advanced knowledge of ECAD software, particularly Cadence Allegro PCB Editor required. • Advanced knowledge of PCB design guidelines and design constraints. • Experience performing layout studies, determining component placement, and helping drive sound architectural decisions. • Experience laying out boards with DDR4 or newer, PCIe Gen 4 or newer, high-speed SerDes, Ethernet, I²C, SPI, and similar interfaces. • Experience with high-speed routing techniques, such as microvias, blind and buried vias, and backdrilling. • Experience working with PCB fabrication shops and PCA contract manufacturers. • Experience with liquid-cooled designs is a plus. • Experience helping define ASIC package ball maps is a plus. • Experience with industry-standard form factors, such as PCIe CEM and Open Compute Project, is a plus. • Experience creating symbols and managing symbol libraries is a plus. Knowledge and Skills: • Ability to read and interpret schematics, datasheets, and layout guidelines. • Ability to work with—and, when necessary, lead—engagements with design partners, including electrical engineers, mechanical engineers, signal-integrity and power-integrity engineers, and others. • Working knowledge of electronics, including signal- and power-integrity issues. • Understanding of EMC principles and best practices for mitigating EMI. • In-depth knowledge of Design for Manufacturing (DFM) and Design for Test (DFT) principles. • Ability to work independently with loosely defined parameters and perform conceptual analysis. • Ability to work successfully with engineers across various geogra