Jobs / United States / Neuralink Corp
Digital IC Design Engineer
Neuralink Corp · 🇺🇸 Austin, Texas, United States; South San Francisco, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 21 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 2 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Neuralink Corp paid sponsored hires in similar roles3 certified filings for “Physical Design and Verification Engineer” (Electrical Engineers) in CA: $134k–$193k, median $165k. Most were filed at wage level II (33%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Neuralink Corp
The US Department of Labor certified 21 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 2 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Neuralink Corp →
About the role
About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Description & Responsibilities: Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred. • Micro-architecture design and RTL implementation of: • Low-power digital signal processors • Low-power general-purpose hardware accelerators • Low-power graphics processing units • Low-power radio MAC/PHY • Low-power serial link MAC/PHY • Design and optimization of hardware/software interface with firmware engineers • Application-specific architecture optimization including: • Complex system modeling for energy and performance benchmarks • Workload analysis and modeling • Energy/performance profiling and analysis • Leveraging architecture-level design trade-offs with process technology and workload type • Balancing cost and performance under manufacturing process variation • Collaboration on silicon bring-up tests with verification engineers Required Qualifications: • Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience • Evidence of exceptional ability in electrical engineering, computer science, or computer engineering • 5+ years of experience in digital design • Expertise in SystemVerilog, C/C++, Python • Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools • Experience in designing digital signal processing pipelines, from algorithm to RTL Preferred Qualifications: • Experience in architecture optimization with process technology customization • Experience in the verification of complex digital systems, using industry standard tools • Experience in the physical design of complex digital systems, using industry standard tools • Experience testing and debugging digital system-on-a-chips • Functional modeling experience and logic verification with SystemVerilog, SystemC/C++ • Experience automating tool flows • Experience with embedded design • Experience in processor instruction set architecture design • Experience in compiler back-end design and customization Expected Compensation: The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees. Base Salary Range: $116,000 — $233,800 USD What We Offer: Full-time employees are eligible for the following benefits listed below. • An