Principal SoC System Architect

Own the system-level and full-chip architecture of next-generation high-end MPU products targeting high-performance applications such as Robotics and Physical AI, industrial networking and control, advanced Vision, multimodal AI processing, and other advanced embedded systems. Define scalable and reusable SoC architectures that integrate heterogeneous compute, Camera/Vision, AI, HMI/Display, memory and interconnect, connectivity, security, safety, and platform-management capabilities into coherent, software-enabled products across multiple market and performance tiers. Translate product strategy, customer use cases, representative workloads, and technology capabilities into architectural decisions that balance performance, power, thermal behavior, area, cost, scalability, software compatibility, implementation feasibility, risk, and time-to-market. Work across a global, multidisciplinary organization spanning Product, business, architecture, HW, SW/FW, verification, implementation, and customer-facing teams. Engage directly with Product Line and Engineering leaders from Director through Vice President level to formulate architecture alternatives, communicate technical and business trade-offs, build alignment, and drive major decisions to timely closure. Principal Accountabilities • Own and drive the system-level and full-chip architecture of next-generation MPU products, from early product definition through silicon bring-up and product validation. Develop clear architecture proposals, align technical and business stakeholders, and drive major decisions to timely closure. • Translate customer use cases, workloads, market requirements, and product strategy into scalable and reusable SoC architectures across multiple product tiers. • Define the full-chip SoC composition, system data and control flows, shared resources, subsystem interfaces, and integration architecture. • Define system requirements and allocate performance, power, thermal, memory, bandwidth, latency, QoS, area, and cost budgets across subsystems. Drive convergence and resolve conflicts. • Define representative concurrent workloads and use quantitative analysis to identify bottlenecks, validate architectural choices, and drive system-resource convergence. • Drive and enable HW/SW co-development through early stakeholder engagement and clear definition of system partitioning, interfaces, requirements, assumptions, and constraints. • Drive architecture trade-offs and implementation-feasibility assessments across performance, power, area, cost, software impact, implementation risk, schedule, and technology constraints. Essential • Extensive experience in the top-level architecture of highly integrated MPU or Application Processor-class SoCs, with demonstrated ownership from product and use-case definition through implementation, silicon bring-up, and product validation. • Broad knowledge of heterogeneous compute, memory hierarchy, cache coherency, interconnect, shared resources, high-speed I/O, system control, power management, security, software-visible architecture, and platform integration. • Ability to translate customer use cases and concurrent workloads into system data and control flows, requirements, KPIs, resource budgets, and architecture decisions. • Experience analyzing system performance through quantitative modeling, identifying bottlenecks and resource constraints, and adjusting the architecture or system configuration accordingly. • Ability to incorporate software and firmware requirements, execution constraints, and ecosystem considerations into HW/SW partitioning, interfaces, and SoC architecture decisions. • Experience assessing full-chip feasibility and driving trade-offs across performance, power, thermal behavior, area, cost, implemen