Memory Layout Technical Lead

• Technical Domain 　Layout design for non-volatile memory (NVM) IP, including Flash, MRAM, and ReRAM • Target Products 　MCUs for automotive, industrial, and IoT applications • Project Overview 　Layout design for NVM IP based on memory cells developed by in-house fabs and foundry partners 　Contribute to PPA (Performance, Power, and Area) optimization of MCU products 　Collaborate with global NVM development teams in Japan and overseas • Responsibilities 　Serve as the technical lead for the memory layout design team 　Develop layout strategies based on IP requirements and circuit specifications 　Lead hands-on layout design and verification activities Renesas is expanding its investment in next-generation embedded NVM technologies and IP development to further strengthen the competitiveness of its MCUs for automotive, industrial, and IoT applications. As embedded NVM IP—including Flash and emerging memory technologies such as MRAM and ReRAM—is a key differentiator for MCUs, demand continues to grow for higher performance, greater capacity, and enhanced reliability. This position is responsible for the layout design of embedded NVM IP for future MCUs. You will have the opportunity to develop a core technology that supports a world-leading MCU business shipping tens to hundreds of millions of units, enabling you to make a significant business impact. Renesas’ embedded NVM IP development organization also actively and continuously submits and presents papers at premier international semiconductor conferences, including ISSCC, the Symposium on VLSI Circuits, and IEDM. Working alongside highly skilled development engineers, you will be able to further deepen your expertise while gaining experience and broader skills across memory technologies. 【MUST】 • Experience in full-custom layout design for non-volatile memory (typically 10+ years) • Experience in building consensus with circuit designers and leading layout design reviews (typically 5+ years) • Experience collaborating with overseas partners in English 【WANT】 • Experience in P&R design • Experience in analog circuit design • Experience in AI-assisted layout design ルネサスは、「To Make Our Lives Easier（人々の暮らしをより豊かで快適にする）」というPurposeのもと、組込み半導体ソリューションを提供するグローバル企業です。世界30か国以上で活躍する21,000人を超えるエンジニアや課題解決のプロフェッショナルとともに、自動車、産業、インフラ、IoT分野における世界最先端のテクノロジー開発に携わり、より安全で、健康的で、環境にやさしく、スマートな未来の実現に貢献しています。    ルネサスでは、「TAGIE（Transparent、Agile、Global、Innovative、Entrepreneurial）」を企業文化の中核としています。TAGIEは、私たちの働き方や成長のあり方、そしてPurposeの実現に向けた取り組みを支える共通の価値観です。この協調的な精神と挑戦するマインドセットが、半導体技術を通じた産業の変革と、世界中の人々の暮らしへの貢献を可能にしています。    私たちは、競争力のある報酬制度に加え、充実した福利厚生をご用意しています。福利厚生の詳細については、選考プロセスの中でご案内いたします。    私たちとともに未来を創造する挑戦に、ぜひ参加しませんか。皆さまからのご応募をお待ちしております。