Jobs / United States / Intel Corporation
Back End( BE) Process Integration Engineer
Intel Corporation · 🇺🇸 US, Oregon, Hillsboro
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Intel Corporation paid sponsored hires in similar roles287 certified filings for “Process Engineer” (Materials Engineers) in OR: $113k–$133k, median $133k. Most were filed at wage level III (87%) — 3 lottery entries, ≈46% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Intel Corporation
The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Intel Corporation →
About the role
Job Details: Job Description: As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. The Intel Logic Technology development (LTD) organizations deliver process technology innovation to drive Intel's product roadmap. Job Responsibilities include but are not limited to: • Develop and define integrated front-end and back-end process flows for new technology nodes. • Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, dielectric, and metrology teams. • Optimize RC (resistance-capacitance) performance. • Establish process windows and integration schemes. • Analyze yield loss and parametric failures. • Perform root cause analysis using statistical tools (SPC, DOE, FMEA). • Drive corrective actions to improve yield and cycle time. • Implement control plans and process monitoring strategies. • Use statistical tools such as: Cpk / Ppk, Control charts, Capability analysis • Ensure margins for electromigration, stress migration, TDDB, time dependent via degradation. • Evaluate impact of process window shifts on reliability. • Support ramp from R and D to high-volume manufacturing (HVM). • Document process specifications and standard operating procedures (SOPs). Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry-relevant job experience, internship experiences, and or schoolwork/classes/research. Minimum Qualifications • PhD in Electrical Engineering, Physics, Applied Physics, Materials Science, Chemical Engineering, Mechanical Engineering, Chemistry, Optics, or a closely related semiconductor field of study. • Hands-on cleanroom experience in one or more of the following: • Interconnect process development (BEOL integration) • Advanced interconnect metallization (Cu, Co, Ru, Mo, or emerging metals) • Electrical characterization of interconnect stacks (RC, EM, reliability) • Cleanroom process development in a university or industry fab environment Preferred Qualifications • Deep understanding of RC delay, electromigration, TDDB, via resistance, and low-k dielectric integration • JMP, Python (scripting/automation), SQL, MATLAB, JSL, TCL — used for real data analysis, not just familiarity • Hands-on experience with dry etch, ALD, PECVD, CMP, metallization in a research or production fab • Demonstrated ability to design experiments, analyze results, and drive process improvements. • Strong analytical and presentation skills — ability to translate complex data into actionable engineering decisions • Familiarity with automation and defect classification systems (e.g., KLA, Applied Materials review tools). • Proven ability to influence outcomes across engineering disciplines without direct authority. • Clear, concise written and verbal communication of complex technical issues to diverse audiences. • Track record of driving projects to completion with accountability in ambiguous, fast-moving environments. Job Type: College Grad Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation