Skills this job asks for
TranslationProduct managementLeadershipEnglishGermanFrenchC++PythonPyTorchTensorFlow
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Sponsorship verdict
Sponsorship possible
One solid signal, not two. Worth applying, and worth asking about sponsorship early.
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✓
Employer is on a government sponsor recordThe US Department of Labor certified 56 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
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The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
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No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
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What Renesas Electronics America INC paid sponsored hires in similar roles1 certified filing for “Senior Staff AI Compiler Engineer” (Software Developers) in TX: $225k–$225k, median $225k.
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Confirmed live todayWhen a source last listed this job as open.
Details and sources
- Employer is on a government sponsor record
- The US Department of Labor certified 56 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
- No salary bar for this route
- H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Renesas Electronics America INC paid sponsored hires in similar roles
- 1 certified filing for “Senior Staff AI Compiler Engineer” (Software Developers) in TX: $225k–$225k, median $225k. Most were filed at wage level IV (100%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.
About the role
Renesas is seeking a Principal AI Software Architecture Engineer to lead the technical direction of next-generation AI software platforms and deployment technologies across embedded and edge computing products. The successful candidate will operate across software architecture, AI model deployment, compiler ecosystems, runtime integration, heterogeneous computing and hardware/software co-design.
Mission
Enable efficient and scalable deployment of AI workloads across diverse hardware platforms while creating a sustainable software foundation for future generations of AI tools, model translation workflows, runtime systems, development environments and customer-facing deployment solutions.
Key Responsibilities
• Define and drive long-term AI software architecture strategy across model translation, compiler, runtime and deployment layers.
• Lead architecture decisions for heterogeneous AI deployment across CPUs, MCUs, MPUs, NPUs, DSPs, GPUs and future accelerator technologies.
• Guide evolution of compiler and runtime technologies, including integration with LLVM/MLIR or equivalent compiler ecosystems where appropriate.
• Collaborate with hardware, software, product, application engineering and customer-facing teams to translate platform needs into executable technical roadmaps.
• Drive hardware/software co-design discussions to influence future AI acceleration and software platform capabilities.
• Mentor senior engineers and technical leads, helping shape architecture thinking across globally distributed teams.
• Represent the technical direction in architecture reviews, roadmap discussions, customer workshops, partner discussions and executive-level technical reviews.
Travel Requirement
Up to 30% international travel may be required. Travel is expected to support global engineering collaboration, architecture reviews, customer workshops, technical roadmap discussions, partner engagement, conferences and executive technical reviews.
Education Requirements
• Master's degree or PhD in Computer Science, Computer Engineering, Electrical Engineering or a related technical field.
• Equivalent depth of technical achievement may be considered where supported by substantial industry experience and recognized architecture leadership.
Experience Requirements
• 15+ years of professional software engineering experience preferred for the target profile.
• 10+ years minimum experience in complex software systems, AI infrastructure, compiler technologies, embedded software, deployment platforms or related domains.
• 5+ years of demonstrated technical leadership, architecture ownership or cross-team technical influence.
• Experience leading architecture decisions that affected multiple teams, product generations, platforms or customer-facing software ecosystems.
• Experience working in globally distributed engineering environments.
Language Requirements
• Fluent English, spoken and written, is required.
• Additional language capabilities, such as Japanese, German, French or other business-relevant languages, are beneficial but not mandatory.
Required Technical Expertise
• Large-scale software architecture and platform evolution.
• AI model deployment workflows and AI software toolchains.
• Compiler ecosystems such as LLVM, MLIR, IREE, XLA, TVM, OpenXLA or comparable technologies.
• Programming expertise in C++ and Python.
• AI frameworks and model formats such as PyTorch, TensorFlow, ONNX and TFLite.
• Runtime integration, performance engineering, profiling, memory optimization and latency/throughput analysis.
• Embedded and edge computing environments, including constraints around memory, power, performance and deployment workflow.
• Heterogeneous hardware architectures including CPU, MCU
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