Semiconductor Test Engineering Team Leader

About Fractile Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts. The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems. The Role We are seeking a senior Semiconductor Test Engineering leader to drive manufacturing test strategy and silicon production readiness for next-generation AI accelerator devices. This role combines deep technical expertise in high-performance compute silicon with leadership responsibility for internal product engineering teams and external development partners. The successful candidate will oversee all aspects of production test development — from DFT strategy and ATE bring-up through silicon characterisation, yield optimisation, advanced packaging test, and high-volume manufacturing ramp — ensuring robust, scalable, and cost-effective test solutions for advanced AI accelerator platforms. Key Responsibilities • Drive the manufacturing test strategy for an AI accelerator chip featuring PCIe Gen6, LPDDR, advanced CMOS nodes, and advanced packaging (e.g., 2.5D/3D, chiplet). • Lead and manage a team of chip test engineers responsible for test planning, test program development, pattern bring-up, silicon characterization, debug, and optimization. • Manage subcontracted test development partners (OSATs, ATE vendors, external engineering services). Includes scoping, technical oversight, schedule tracking, and quality control of deliverables. • Define and drive test software architecture, DFT usage, and test pattern development strategies for high-speed logic, SRAM, DRAM, and High Speed IO blocks. • Work closely with design, DFT, product engineering, packaging, and validation teams to ensure robust test coverage, manufacturability, and yield ramp success. • Oversee test development for high speed interfaces such as PCIe Gen6 and multi-GHz LPDDR. • Guide development of structural and functional test content (scan, MBIST, JTAG, HSIO tests, system-level tests). • Lead silicon bring-up and development on ATE: correlation, failure analysis, shmooing, corner testing, stress testing, and yield improvement activities. • Define KPIs and metrics for subcontractor performance, test coverage, yield, time-to-test, and cost optimization. • Drive continuous improvement in test methodologies, automation, data analytics, and debug infrastructure. • Ensure robust test flows for advanced packaging (thermals, interposer/bridge connections, TSV integrity, die-to-die IO testing). • Support qualification, reliability testing, and high-volume manufacturing transfer. Required Qualifications • 8+ years in semiconductor test engineering, including leadership or technical lead roles. • Deep experience with ATE test development (e.g., Advantest 93K, Teradyne). • Strong understanding of DFT (scan, ATPG, LBIST, MBIST), mem