Staff/ Senior Staff Engineer, STA

We are looking for a highly motivated STA Engineer to join our VLSI design team. The ideal candidate will be responsible for driving timing closure and signoff readiness for block-level and full-chip designs across all operating modes and process corners. This role involves developing and validating timing constraints, performing comprehensive timing analysis, and collaborating closely with RTL Design, Synthesis, Clock Tree Synthesis (CTS), and Physical Design teams to identify, debug, and resolve timing violations. The successful candidate will play a key role in achieving timing convergence and delivering high-quality silicon through successful tapeout. This position offers an opportunity to work on advanced semiconductor technologies and contribute to the development of high-performance, power-efficient SoCs. What You'll Do • Perform block-level and full-chip Static Timing Analysis (STA) across all modes and corners in MMMC environments. • Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations. • Develop, validate, and maintain timing constraints, including SDC creation, review, and signoff readiness. • Partner closely with RTL Design, Synthesis, CTS, Physical Design, and Signoff teams to achieve timing closure goals. • Drive timing closure through ECO implementation, timing optimization, and timing convergence activities. • Perform pre-layout and post-layout timing analysis and support tapeout signoff requirements. • Analyze timing impact due to process, voltage, and temperature (PVT) variations and variation-aware methodologies. • Review and validate timing exceptions including false paths, multicycle paths, case analysis, and clock definitions. • Identify root causes of timing violations and recommend effective optimization strategies. • Participate in cross-functional design reviews and provide guidance on timing-related issues. • Generate timing reports, closure metrics, and signoff summaries for project stakeholders. • Support design quality improvements by establishing and enhancing STA methodologies, automation, and best practices. Required Qualifications • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related field. • 7 to 13 years of hands-on experience in Static Timing Analysis (STA) and timing closure for block-level and/or full-chip semiconductor designs. • Strong understanding of CMOS fundamentals, timing concepts, and end-to-end semiconductor design flow. • Solid experience with setup/hold analysis, path-based analysis (PBA), and timing signoff methodologies. • In-depth knowledge of OCV, AOCV, POCV, timing derates, uncertainty modeling, and MMMC analysis. • Strong understanding of clock tree concepts including clock latency, skew, jitter, uncertainty, and clock propagation. • Experience developing and debugging timing constraints and timing exceptions. • Good understanding of SDC syntax, false paths, multicycle paths, generated clocks, and case analysis. • Hands-on experience with timing closure techniques and ECO methodologies. • Proficiency with industry-standard STA tools such as Synopsys PrimeTime and/or Cadence Tempus. • Good scripting and automation skills using Tcl, Perl, Python, or similar languages. • Strong analytical, debugging, and problem-solving skills with the ability to independently resolve complex timing issues. • Excellent communication and collaboration skills in cross-functional engineering environments. Preferred Qualifications • Experience with low-power timing analysis and UPF/CPF-aware STA methodologies. • Familiarity with signal integrity (SI)-aware timing analysis, crosstalk analysis, and IR-drop-aware timing closure. • Understanding of a