Senior Staff Engineer, Physical Design

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications. Renesas India is seeking an experienced Staff / Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies. Key Responsibilities • Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality • Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution • Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture • Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency • Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption • Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure • Proactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions 7+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs • Strong expertise in: • Timing closure and constraint management • Congestion analysis and resolution • Power integrity and power-aware physical implementation • Block and subsystem-level physical design flows • Solid understanding of SoC-level floorplanning and clocking methodologies, including: • Clock domain partitioning • Clock tree architecture • Skew management • Clock gating (Candidate is expected to collaborate effectively at the SoC level, not lead these activities.) • Hands-on experience with industry-standard tools such as: • Synopsys ICC2, Fusion Compiler, PrimeTime • Cadence Innovus, Tempus, Certus • Signoff and analysis platforms • Proficiency in scripting and automation using Tcl, Python, and/or Perl • Deep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams • Strong understanding of low-power design techniques and power-aware implementation methodologies Education • BTech or MTech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in mor