Jobs / United Kingdom / Quantum Motion Technologies Limited
Quantum Motion Technologies Limited
Senior IC PDK Development Engineer
London, UK
Posted 25 days ago
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Sponsorship possible
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- Employer is on a government sponsor recordThis employer holds a UK sponsor licence (Skilled Worker, A rating).
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- Can’t check pay against the visa rulesNo salary stated. UK Skilled Worker visa needs at least £41,700 a year (new-entrant (under 26, recent Student/Graduate visa) or STEM PhD: £33,400).
- Confirmed live todayWhen a source last listed this job as open.
Details and sources
- Employer is on a government sponsor record
- This employer holds a UK sponsor licence (Skilled Worker, A rating). Source: Register of licensed sponsors (UK Home Office).
- Can’t check pay against the visa rules
- No salary stated. UK Skilled Worker visa needs at least £41,700 a year (new-entrant (under 26, recent Student/Graduate visa) or STEM PhD: £33,400). Source: https://www.gov.uk/skilled-worker-visa/when-you-can-be-paid-less, rules effective 2025-07-22.
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About the role
• Development of custom PDK elements from scratch, including Schematic symbols, Layout SKILL PCells, and custom DRC and LVS decks.
• Development, qualification, and maintenance of custom Calibre SVRF rule decks tailored for non-standard layout constraints and cryogenic CMOS layout considerations.
• Integrate tier-1 foundry PDKs into Cadence Virtuoso, creating customized library extensions, layer maps, and device callbacks.
• Work closely with IC designers and layout engineers to establish best practices for physical verification and layout automation.
• Document own work for peer review and evaluate the layout and enablement work of other team members.
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• Industry degree qualification in Electronic Engineering, IC Layout, Computer Science, or a related physical science/engineering field.
• 5+ years of hands-on industry experience in IC PDK Development and PDK enablement flow management.
• Demonstrated proficiency in Cadence SKILL PCell coding and Virtuoso PDK customization.
• Demonstrated proficiency in Siemens Calibre Physical Verification tools and SVRF Rule writing (specifically for DRC and LVS decks).
• Proven hands-on experience in complex DRC and LVS error debugging within analog/mixed-signal or custom digital layout environments.
• Strong analytical and problem-solving skills with a high level of self-management, self-motivation, and willingness to engage actively in peer code and layout reviews.
• Excellent verbal and written communication skills to collaborate effectively across multidisciplinary physics and IC engineering teams.
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• Demonstrated experience with advanced deep-submicron CMOS nodes (40nm, 28nm, or below), including familiarity with layout-dependent effects (LOD, WPE, OSE, etc.).
• Expert knowledge of the Cadence Virtuoso Design Environment and Cadence SKILL / SKILL++ programming.
• Expert knowledge of the Siemens Calibre Physical Verification Environment.
• Familiarity with MOSFET device modeling integration (e.g., BSIM, Verilog-A) or cryogenic device enablement.
• General awareness or curiosity regarding semiconductor quantum dots or silicon spin qubit fundamentals.
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• Be part of a creative, world-leading team
• Competitive salary and share options scheme
• Contributory pension scheme
• Private Medical Insurance
• Life Assurance
• Cycle-to-work Scheme
• Flexible working
• Central London location (Islington)
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