Jobs / United States / Nvidia Corporation

Nvidia Corporation

ASIC Methodology, Flow and Integration Engineer

2 Locations Posted today

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Sponsorship verdict

Sponsorship possible

One solid signal, not two. Worth applying, and worth asking about sponsorship early.

  • Employer is on a government sponsor recordThe US Department of Labor certified 2,374 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • What Nvidia Corporation paid sponsored hires in similar roles628 certified filings for “Engineer Senior ASIC” (Electronics Engineers, Except Computer) in CA: $168k–$216k, median $188k.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
Employer is on a government sponsor record
The US Department of Labor certified 2,374 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
What Nvidia Corporation paid sponsored hires in similar roles
628 certified filings for “Engineer Senior ASIC” (Electronics Engineers, Except Computer) in CA: $168k–$216k, median $188k. Most were filed at wage level IV (75%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

About the role

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for ASIC Flow and Integration Engineer to drive design methodology, automation, and integration for our High Speed IO team. What you'll be doing: As one of the primary methodology engineer, you’ll work across all NVIDIA-delivered projects, owning the integration process and collaborating with global teams to define and implement best-in-class methodologies. You’ll operate beyond RTL coding—building infrastructure and systems that are modular, reusable, and easily deployable across diverse silicon platforms. During the course of a project you would end up driving the following aspects of: • Own the full-chip and block-level integration process across multiple NVIDIA SoC and GPU projects. • Stitch together RTL units and ensure seamless connectivity, and hierarchy management. • Define and evolve internal design methodologies to improve scalability, quality, and turnaround time. • Build automation pipelines using Python/Perl to streamline integration, debug, and delivery. • Develop modular and reusable systems that can be easily delivered and adapted across different SoC and GPU architectures. • Collaborate extensively with RTL, verification, physical design, and architecture teams to ensure flow compatibility and design readiness. • Drive full-chip debug efforts, connectivity, and functional issues across multiple hierarchies and technology nodes. • Contribute to continuous improvement of internal standards and mentor engineers on flow usage and integration practices. What we need to see: • BS or B.Tech or MS or M.tech in EE, ECE, CS, or equivalent degree with 1+ year or more experience in design integration and methodologies for ASIC design. • Comprehensive understanding of IP development flows, build flows is a must • Excellent influencing skills resulting in collaboration with cross-cultural, multi geography and matrixed teams • Good debugging, analytical and problem solving skills • Great interpersonal skills and ability to work as an excellent teammate • Working exposure with AI tools like Claude and Cursor would be a plus We have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology and improving the state of art, we want to hear from you! Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/ #LI-Hybrid

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