Sponsorship verdict
Sponsorship possible
One solid signal, not two. Worth applying, and worth asking about sponsorship early.
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✓
Employer is on a government sponsor recordThe US Department of Labor certified 123 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
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The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
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No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
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✓
What Samsung Semiconductor INC paid sponsored hires in similar roles41 certified filings for “Senior Engineer” (Software Developers) in CA: $141k–$207k, median $174k.
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✓
Confirmed live todayWhen a source last listed this job as open.
Details and sources
- Employer is on a government sponsor record
- The US Department of Labor certified 123 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
- No salary bar for this route
- H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Samsung Semiconductor INC paid sponsored hires in similar roles
- 41 certified filings for “Senior Engineer” (Software Developers) in CA: $141k–$207k, median $174k. Most were filed at wage level II (53%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.
About the role
Please Note:
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Advancing the World’s Technology Together
Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.
What You’ll Learn
• Project Overview: Physical memory is a bottleneck for AI systems; power and heat decide how fast AI models can run. Our lab is building a simulator tool to aid memory architecture and packaging teams in their work, allowing them to visualize how their designs impact power consumption and heat generation quickly without needing a physical prototype and hours of computation. As a software intern, you will gain an understanding of the entire data pipeline as you develop this tool, improving its features or user experience.
• Skills You’ll Learn:
• Simulation Infrastructure
• User Interface Development
• Power & Thermal Engine Development
What You’ll Do
Samsung’s Power & Thermal Lab is seeking a software engineering intern to contribute in the development of our power and thermal simulation tool.
We are a small, fast ‑ moving team where direct ownership and minimal busywork empower every member to tackle the same real‑world problems. Working with authentic data, real partners, and production‑grade results, our contributions flow straight into platforms used across the company.
As an intern, you will support research and product teams across multiple projects, including providing end ‑ to ‑ end simulation , regression testing , and data ‑ pipeline management . You will work on real projects with tangible results , receive mentorship, and help shape the scope of work in a collaborative environment where hardware, software, and thermal experts work side‑by‑side on next‑generation AI memory technologies.
Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy
Reports to: SVP, R&D (Power & Thermal Lab)
• Build automation pipelines for simulation runs, regression testing, and result tracking.
• Implement and optimize a trace‑driven power‑thermal simulation engines.
• Generate transient power maps, perform spatiotemporal hotspot analysis, and interface with reduced‑order/CFD‑calibrated thermal solvers.
• Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
• Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
• Define power-relevant functional states (transaction/state-based abstraction).
• Calibrate models using synthesis‑assisted anchors and validate against RTL/gate‑level and silicon data.
• Integrate IP‑level power macromodels into system‑level simulations.
• Manage time‑indexed simulation flow across power and thermal domains.
• Complete other responsibilities as assigned.
What You Bring
• Pursuing Masters or PhD in Computer Science, Electrical and Computer Engineering, or related major.
• Must have at least 1 academic quarter/semester remaining
• C++, scripting workflows in Python or Bash, SystemC and/or transaction-level modeling.
• Systems‑level software‑engineering skills.
• RTL design, synthesis and ana
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