ASIC Design Verification Engineer - Slingshot

ASIC Design Verification Engineer - Slingshot    This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: About the Team and the Project Our team develops HPE Slingshot, an industry-leading interconnect used in some of the world's largest HPC and AI systems ( HPE Slingshot interconnect ). As a Design Verification Engineer, you will work alongside experienced architects, logic designers, and verification engineers on the switch and NIC ASICs for a future generation of Slingshot. You will own the verification of blocks from test plan through sign-off, grow your technical depth with support from senior engineers, and help put emerging agentic AI workflows to work on complex engineering problems. We are looking for engineers who want to work at the leading edge of high-performance interconnects for HPC and AI, who take ownership of their work, and who want to grow beyond a narrowly defined test-writing role. Job Description In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage closure, and sign-off reviews. Responsibilities • Follow and improve the team's design verification methodology. • Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus. • Plan and implement block level scoreboards and checkers to verify functional behavior. • Write and analyze functional coverage to find verification gaps and drive coverage closure. • Triage regression failures and identify logic bugs, while driving bug closure. • Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process. • Work with designers, architects, and project leads on design status, verification progress, and issue resolution. • Work independently as a member of a project team that includes other VLSI engineers and internal and outsourced development partners. • Provide guidance and mentoring to less experienced staff members. Education and Experience Required • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent. • 5+ years of experience in VLSI design, verification, or implementation. Knowledge and Skills • Strong knowledge of SystemVerilog and of OVM or UVM methodologies. • Strong knowledge of programming and scripting languages, hardware description languages, and electronic design automation (EDA) tools. • Strong analytical and problem solving skills. • Ability to be self-directed in a distributed team environment. • Strong written and verbal communication skills; mastery in English. Preferred Skills • Experience verifying high-speed networking, switching, or NIC ASICs. • Experience with agentic AI coding tools and workflows applied to verification. • Experience with Python, Perl, Tcl, or another scripting language in Linux development environments. • Experience wo