VLSI Physical Design Engineer

VLSI Physical Design Engineer    This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Job Family Definition: Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation, and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication. Management Level Definition: Contributions include applying developed subject matter expertise to solve common and sometimes complex technical problems and recommending alternatives where necessary. Might act as project lead and provide assistance to lower level professionals. Exercises independent judgment and consults with others to determine best method for accomplishing work and achieving objectives. Responsibilities: • Perform static timing analysis for hierarchical designs at both partition and full-chip levels. • Create, validate, and maintain timing constraints and timing budgets for design and process requirements. • Drive timing closure for partition-level and full-chip designs, including setup, hold, clock, I/O, and test timing. • Analyze timing reports, identify critical paths, and implement fixes to achieve performance, power, and area objectives. • Perform synthesis, netlist quality checks, and formal verification. • Support chip partitioning, floorplanning, and physical design implementation. • Create and manage functional engineering change orders (ECOs). • Develop flow automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff, often using AI to improve methodologies. • Partner with cross-functional engineering teams to promote physical-design-aware architecture and implementation. • Review design and project activities for compliance with ASIC technology, methodology, and development standards. • Collaborate with external physical design partners to close timing and complete back-end flows. • Provide technical guidance and mentoring to less-experienced engineers and contribute to continuous improvement across the design organization. • Education and Experience Required: • Bachelor's or Master's degree in Electrical Engineering, Computer engineering or equivalent • 1-6 years of experience in VLSI design, verification, or implementation Knowledge and Skills: • Strong knowledge of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture • Experience with one or more of the following: • Static timing analysis and timing signoff • Timing constraints and validation • Synthesis and netlist quality analysis • Fo