Intern, SRAM Design Engineer

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities. What You’ll Learn • Project Overview: Understand SRAM compiler, bit-cells, write/read operation and analysis with simulations • Skills You’ll Learn: • Different type of SRAM bit-cells • SRAM compiler flow and write/read operations • SRAM design procedure • Compose schematics and run simulations and check/debug What You’ll Do The SRAM Lab is seeking an intern to support the development, simulation, and optimization of SRAM circuits. Our lab designs, develops, and optimizes advanced SRAM circuits for next‑generation semiconductor products. We integrate rigorous circuit analysis with innovative layout strategies to deliver memory solutions that satisfy the stringent power, performance, and area (PPA) requirements of future AI and mobile ecosystems. As an intern, you will contribute to our full‑stack SRAM projects—covering architecture, schematic design, and silicon‑level verification—while researching novel architectures that boost computing‑platform efficiency and ensure seamless SoC compatibility. Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy Reports to: Sr. Director, SRAM Design • Assist in the design and simulation of SRAM circuits using industry-standard EDA tools • Perform transistor-level schematic design for SRAM bitcell, sense amplifiers and peripheral circuits • Conduct simulations to verify functionality, timing, power and reliability of SRAM design • Document design processes, simulation results, and findings in technical reports or presentations • Complete other responsibilities as assigned. What You Bring • Pursuing Masters, or PhD in Electrical or Electronic Engineering preferred • Must have at least 1 academic quarter/semester remaining • Basic understanding of CMOS circuit design and semiconductor devices physics • Familiarity with SRAM or memory design concepts (preferred but not mandatory) • Experience with EDA tools such as Cadence Virtuoso, hspice, finesim and spectre • Proficiency in scripting languages (e.g. Python, Perl or TCL) • You’re inclusive, adapting your style to the situation and diverse global norms of our people. • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. • You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. • Innovative and creative, you proactively explore new ideas and adapt quickly to change. What We Offer The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in