Sponsorship verdict
No sponsorship evidence yet
No government record and no wording either way. Not a refusal: ask the recruiter.
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No government sponsor record hereThis employer posted directly and does not match a government sponsor register.
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The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
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Can’t check pay against the visa rulesNo salary stated. UK Skilled Worker visa needs at least £41,700 a year (new-entrant (under 26, recent Student/Graduate visa) or STEM PhD: £33,400).
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Confirmed live todayWhen a source last listed this job as open.
Details and sources
- Can’t check pay against the visa rules
- No salary stated. UK Skilled Worker visa needs at least £41,700 a year (new-entrant (under 26, recent Student/Graduate visa) or STEM PhD: £33,400). Source: https://www.gov.uk/skilled-worker-visa/when-you-can-be-paid-less, rules effective 2025-07-22.
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Before you apply
Sponsorship unknown
No register record and no sponsorship wording in the posting. Worth asking the employer before investing significant time.
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About the role
At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient . Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.
Job title: Analog Layout Engineer (Lead)
Location: EU/CH/UK
Responsibility
• Position in custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip to chip communication links (SerDes up to and beyond 28Gb/s and/or memory IO) in advanced semiconductor technology nodes
• Layout and verification of very high-speed analog circuits
• Interact closely with the design team to understand requirements and implement solutions
• Support IP and chip level integration
• Support and interact with customers on requirements, and IP delivery
• Exposure to flip-chip package technologies
Experience
• 10-15 years of relevant experience.
• Must have experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits
• Must have expertise in layout of high-speed /frequency circuits like amplifiers, oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, buffers, regulators, filters, data converters, etc.
• Understanding of layout approaches and techniques for high-speed circuits, matching constraints, minimization of parasitics, power grids and ESD requirements
• Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm
• User of EDA tool for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc.
Skills
• Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player
• Manage workload and schedules and report to internal management team
• Background in Semiconductor Physics
Education
• Graduate in E.E.
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