Jobs / Israel / Nvidia Corporation

Nvidia Corporation

Senior STA Engineer

Israel, Tel Aviv Posted today

Apply on employer site ↗ Tailor my CV first Source: Company careers site

Optional: we can tailor a CV and cover letter for this job from your real experience first (the first one is free).

Sponsorship verdict

No sponsorship evidence yet

No government record and no wording either way. Not a refusal: ask the recruiter.

  • No government sponsor record hereNo government sponsor record covers this employer in this country.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • Can’t check pay against the visa rulesWe don’t have visa salary rules for this country yet.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

Before you apply

Sponsorship unknown

No register record and no sponsorship wording in the posting. Worth asking the employer before investing significant time.

These come from the posting’s own wording. Read the original listing to confirm. See better-fit alternatives →

About the role

NVIDIA is seeking a Physical Design and Timing Engineer to join our silicon implementation team. This role focuses on timing analysis, timing closure, and signoff quality across complex ASIC and SoC designs. You will work closely with physical design, front-end design, methodology, and CAD teams to drive robust implementation at advanced process nodes. This is a strong fit for an engineer who enjoys deep analysis, problem solving, and improving quality at block and full-chip levels. What you’ll be doing: • Drive static timing analysis and timing closure for block and/or full-chip designs. • Develop, review, and debug timing constraints, scenarios, and signoff checks. • Analyze setup, hold, noise, and variation-related timing issues and drive closure with cross-functional teams. • Partner with physical design engineers on floorplan, CTS, route, ECO, and convergence activities. • Review reports, identify root causes of violations, and recommend high-quality fixes with minimal design impact. • Improve timing methodology, automation, and debug efficiency using Tcl, Perl, and/or Python. What we need to see: • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience. • 5+ years of experience in ASIC or SoC physical design, timing analysis, or implementation. • Strong understanding of static timing analysis fundamentals, timing constraints, and timing closure. • Hands-on experience with industry-standard EDA tools such as PrimeTime, ICC2, Innovus, Tempus, or equivalent. • Experience debugging setup/hold violations, clocking issues, and ECO impacts. • Solid scripting skills in Tcl plus familiarity with Perl or Python. • Good communication skills and ability to work across design, CAD, and verification teams. Ways to stand out from the crowd: • Experience with advanced-node implementation and signoff. • Knowledge of MMMC flows, SI, OCV/AOCV/POCV, and power-aware timing analysis. • Experience improving timing methodology or developing reusable automation. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided a reasonable accommodation to participate in the job application or interview process, perform essential job functions, and receive other benefits and privileges of employment. Please contact us to request accommodation.

Apply on employer site ↗