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Northrop Grumman Systems Corporation

FPGA Engineer

United States-Illinois-Rolling Meadows Posted today

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No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

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About the role

RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: Yes CLEARANCE TYPE: Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. We are seeking talented FPGA Design Engineers to join our growing team in Rolling Meadows, Illinois. The Multidomain Sensing, Targeting, and Survivability Division (MSTS), located in the Northwest Chicago suburbs, develops operational Electronic Warfare (EW) and targeting systems that provide situational awareness, self-protection, and offensive electronic attack capability to platforms across the spectrum from visible light IR to millimeter wave RF. By joining us, you’ll work on projects that help safeguard our nation related to land forces, rotary wing survivability systems, international and U.S. military electronic warfare systems, communications systems, missile warning systems and sensors, infrared counter-measure systems (IRCM), automatic test equipment, modeling and simulation, and situational awareness programs. As an FPGA Design Engineer, you will join a diverse, high-performing team responsible for the end-to-end development of advanced RF and EO/IR products. You will contribute across the FPGA development lifecycle, including requirements analysis and refinement, system and FPGA architecture, RTL design and coding, testbench development, verification, synthesis, implementation, timing closure, hardware integration, qualification, production support, and troubleshooting. You will develop FPGA-based digital subsystems integrated into circuit card assemblies, working closely with systems, software, hardware, and integration & test engineers. Designs utilize FPGA technologies from major vendors including AMD Xilinx, Intel, and support high-speed interfaces, RF and EO/IR signal-processing chains, controls, data links, embedded processing, and processor interfaces. This position will be full-time and on-site at our Rolling Meadows, IL. location. The qualifications for the FPGA Design Engineer are below. Basic Qualifications for FPGA Design Engineer • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related engineering discipline with a minimum of 2 years of relevant FPGA/ASIC design experience; or a master’s degree with relevant experience. • Solid understanding of VHDL, Verilog, or SystemVerilog for RTL design and verification. • Experience developing synchronous RTL, including state machines, control logic, data paths, clocks, and resets. • Experience developing or modifying RTL testbenches and debugging simulation failures. • Familiarity with the overall FPGA development flow, including RTL simulation, synthesis, place and route, timing analysis, and generation of FPGA programming files. • Experience with at least one major FPGA device architecture and its associated development toolchain, such as AMD Xilinx devices with Vivado or Intel FPGA devices with Quartus. • Experience with FPGA electronic design automation tools, such as ModelSim/Qu

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