Principal PCS/PMA RTL Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Principal PCS/PMA RTL Design Engineer Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards such as Ethernet, PCIe, UCIe, and UALink. You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs. You will work with experienced architects and design engineers to translate microarchitectural specifications into robust, synthesizable RTL. You will collaborate closely with SerDes/analog, verification, physical design, DFT, firmware, systems, and validation teams to deliver reliable designs through synthesis, timing closure, tapeout, and silicon validation. This is a hands-on opportunity for an engineer who wants to build expertise in multi-protocol, multi-lane PHY digital design and contribute to products that enable next-generation AI and cloud infrastructure. Key responsibilities PCS/PMA RTL design and implementation • Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols. • Implement PCS functions such as line encoding/decoding (64b/66b, 128b/130b, 8b/10b), scrambling/descrambling, block and word alignment, lane deskew and reordering, gearboxes, elastic buffers/FIFOs, and rate adaptation. • Implement forward error correction (e.g., RS-FEC/KP4, FEC framing, interleaving), plus the related error counters and status logic. • Implement PMA digital interface logic, including SerDes datapath interfaces (PIPE, SerDes-facing parallel interfaces, UCIe PHY/raw-die interfaces), clock and data recovery (CDR) control interfaces, equalization and link-training control (e.g., PCIe LTSSM equalization, Ethernet auto-negotiation/link training), and calibration and adaptation control. • Design lane-level and multi-lane logic, including lane bonding, polarity and lane reversal, PRBS generation/checking, loopback modes, and BIST features. • Translate architectural and microarchitectural specifications into datapaths, control logic, state machines, register interfaces, and protocol logic. • Design reusable, configurable RTL modules that support multiple protocols, data rates, and lane configurations. • Integrate internal and third-party IP (including analog/mixed-signal PHY macros) while following established design and coding methodologies. • Participate in design reviews and contribute to improvements in RTL quality, reuse, latency, performance, power, and area. Verification and design quality • Collaborate with design verification engineers to define functional requirements, test plans, and coverage goals, including protocol compliance (IEEE 802.3, PCI-SIG, UCIe, UALink specifications). • Debug simulation failures using waveform analysis, assertions, regression results, and root-cause analysis. • Support lint,