ML Silicon Performance Lead

ABOUT THE TEAM: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. ABOUT THE ROLE: We’re looking for an ML Silicon Performance Lead to drive hardware/software co-design for our silicon architecture. You will work across models, kernels, compilers, and silicon to shape how ML workloads map to hardware—and how the hardware should evolve to support them. Your work will connect model and workload requirements with compute, memory, and specialized acceleration capabilities to maximize performance, efficiency, and scalability across current and future generations of AI silicon. You’ll partner closely with ML research, compiler, and silicon architecture teams to jointly develop software approaches and hardware capabilities. From kernel mapping and quantization to new data structures and specialized IP, you’ll evaluate hardware and software tradeoffs to improve performance, efficiency, and utilization across large-scale AI workloads. Through performance modeling, simulation, and hands-on optimization, you’ll guide architectural decisions and validate improvements on representative workloads. IN THIS ROLE, YOU WILL: - Drive hardware/software co-design across ML research, compiler, and silicon teams, jointly shaping kernel implementations and hardware capabilities to meet workload performance and efficiency goals. - Partner with ML research to translate model and workload needs into kernel performance targets and compute, memory capacity, and bandwidth requirements, feeding hardware constraints and opportunities back into model and algorithm choices. - Map and optimize ML kernels for architecture, using insights from data movement, memory hierarchy, and execution efficiency to guide both software improvements and hardware design. - Co-design support for new data structures and quantization formats across kernels, compilers, and silicon, balancing model quality, numerical behavior, performance, power, and implementation cost. - Define and help develop specialized acceleration IP, working with compiler and silicon partners to determine the right division of functionality across software, instructions, and dedicated hardware. - Drive ML performance modeling and simulation with the compiler team to compare hardware/software design options, expose bottlenecks, and quantify end-to-end benefits on representative workloads. - Partner with the Silicon Architecture lead and silicon team to specify and validate new IP, using kernel and simulation results to refine requirements and prioritize architectural improvements. YOU MIGHT THRIVE IN THIS ROLE IF YOU: - Have deep experience with ML accelerator architecture and how compute resources, memory systems, and data movement shape workload performance. - Can translate model-level behavior into concrete kernel requirements and hardware design decisions. - Have built or used accelerator performance models and simulators, and know how to validate their assumptions and interpret their limitations. - Have hands-on experience optimizing ML kernels, including identifying bottlenecks and improving utilization, locality, and execution efficiency. - Understand quantization and numerical formats, including their implications for model quality, memory bandwidth, compute efficiency, and hardware support. - Have experience with hardware/software co-design and