SCG ArchDesign Engineer - New College Grad 2027

Silicon Co-Design Group (SCG) is a wide-ranging, multi-functional, integral team at NVIDIA. We sit at the crossroads of design, architecture, marketing, operations, and productization. Our contributions span from the arch stage and extend to defining final products. We architect innovative solutions for Datacenter, Server, Gaming, Robotics, Automotive, and Embedded markets. We do all of this with an eye on making groundbreaking, impactful market disruptions! We are looking for a ArchDesign Co-Design Engineer(NCG),who approaches silicon co-design through prototyping and design of experiments: we build the vehicles, measurement plans, and analyses that show how power, performance, noise, circuit margin, and binning actually behave, then turn those results into tools and data pipelines that architecture, firmware, and manufacturing can use. This is a highly visible, multi-functional role. Success in this role requires owning silicon truth on messy bring-up and data: deciding what an experiment proved, catching when a number or a model is wrong, and leaving behind reusable methods other teams can ship against.   What you will be doing: • Standing up silicon co-design prototypes and measurement setups that expose power-rail noise, circuit margin, performance, and binning behavior — from first bring-up through a repeatable experiment others can rerun. • Planning and executing design of experiments (DOE): choosing factors and ranges (voltage, frequency, workload, temperature, process), defining sample plans and success criteria, and analyzing main effects and interactions so results are usable, not just collected. • Building Python pipelines and analyses that turn prototype, DOE, simulation, and characterization data (power, noise, Vmin/Fmax, binning yield) into traces, summaries, and inputs for firmware tuning, product specs, and manufacturing limits — with checks for schema, units, corners, and SKU mapping. • Partnering with architecture, design, validation, and firmware to add debug hooks, iterate the prototype, and document what the experiment proved versus what still needs silicon. • Using secure, traceable, validated AI-assisted workflows for experiment planning, analysis, and documentation, with human oversight on any conclusion that could affect limits, bins, or specs.   What we need to see: • MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field. • 2+ years in a related silicon, validation, characterization, productization, or engineering-tools role (SoC, GPU, CPU, or similar). • Working knowledge of silicon speed/power/quality concepts — for example DVFS, Vmin/Fmax, shmoo, PDN/noise, binning, or guardband — and comfort learning DOE and prototype bring-up in a co-design setting. • Hands-on experience with at least one of: lab or post-silicon bring-up, experiment or characterization campaigns, manufacturing test/limits, or tools/pipelines that consume chip data. • Proficiency in Python (or similar) for data analysis, automation, and validation; comfort with Git and structured test/regression. SQL or lightweight dashboards are a plus. • Ability to turn an ambiguous silicon question into a measurable experiment, communicate clearly across teams, and write notes others can execute from. • Strong AI-enabled skills and thinking — use AI to accelerate analysis, exploration, and documentation while maintaining rigor, originality, and judgment that do not come from AI.   Ways to stand out from the crowd: • You have run a test-chip, prototype vehicle, or characterization DOE and can explain what you would change in the next matrix. • Direct experience on GPU/SoC/CPU power, performance, binning, PDN/noise, or sim-to-silicon correlation. • You have shipped an internal tool, dashboard, or d