Senior/Lead VLS Engineer - Global Circuits

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value. About the team div]:bg-bg-000/50 [&_pre>div]:border-0.5 [&_pre>div]:border-border-400 [&_.ignore-pre-bg>div]:bg-transparent [&_.standard-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.standard-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8 [&_.progressive-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.progressive-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8"> _*]:min-w-0 gap-3 [&_>_*:last-child]:mb-0 print:block print:[&_>_:where(:not(:first-child))]:mt-3 standard-markdown"> The team integrates SambaNova's AI accelerators into rack scale systems and gets them deployed in customer datacenters. We handle the racking and stacking of tightly integrated network, power, and compute equipment in both prototype and production environments, and we take rack solutions through prototyping into mass production so they stay manufacturable and serviceable at scale. We work with architects, engineering teams, customer datacenter teams, sales, and marketing, and we manage vendor relationships to line the equipment up with our current and future roadmap. Position Overview We are looking for a Senior / Lead VLSI Design Engineer to serve as the architect and hands-on owner for various global circuit areas including custom clocking, low-power design technqiues and power distribution integrity while championing chip-level PLL, IO, ESD, and Latch-Up strategy and Integration. In this role, you will design and optimize ultra-low-jitter, low-skew and low-power custom clock distribution networks from the ground up as well as in-depth power analysis and developing low power solutions. Utilizing your deep hands-on background in PLL, ESD, Latch-Up, and IO design, you will partner with specialized IP teams to ensure seamless SoC integration and drive full chip compliance across strict performance and reliability targets. Key Responsibilities • Architect, design, and perform transistor level circuit design and optimization of custom ultra-low-jitter, low-skew chip-level clock distribution networks (H-trees, grids, meshes or hybrid topologies) • Perform comprehensive signal integrity (SI), power integrity (PI), jitter, skew, and EM/IR analyses across all chip-level clock distribution networks • Involved in low-power design methodology and power analysis of key components • Power distribution integrity analysis • Collaborate closely with Physical Design teams on floor-planning, custom routing, shielding strategies, and Clock Tree Synthesis (CTS) guidelines • Partner with IP teams to select, evaluate, and integrate custom IO pads, level translators, primary/secondary ESD clamps, and rail protection structures specified by the ESD/Latch-Up methodology • Drive pre-silicon chip-level reliability and clock timing sign-off before tape-out and support for post silicon bring-up. Minimum Qualifications • Bachelor’s or Master’s degree in Electrical Engineering or Microelectronics. • 8+ years of custom analog/mixed-signal VLSI design experience in advanced process nodes (FinFET / GAA, e.g., 7nm, 5nm, 3nm, 2nm). • Experience designing custom clock networks, low-powe