WPM Integration: Defect Engineer

Job Details: Job Description: The Wafer Packaging Manufacturing organization is a global team at the heart of Intel's advanced packaging technology and high-volume manufacturing. Our vision is clear: optimize advanced packaging HVM processes end-to-end to maximize yield, quality, and customer satisfaction. WPM spans a broad and critical portfolio - including EMIB and Foveros wafer processing, TSV reveal, C4 bumping, Die Prep, and Wafer Level Assembly - supporting Intel's most strategic technologies across multiple sites worldwide   As a WPM Advanced Packaging Defect Reduction Engineer, you will play a pivotal role in protecting yield and elevating defect performance across some of the world's most advanced semiconductor packaging processes. Partnering with module engineering, QNR, manufacturing operations, and yield teams across our global network, you will bring together HVM manufacturing expertise with the technical rigor of a development organization to deliver impactful, lasting solutions. At WPM, we are more than a team - we are an organization that learns, grows, and succeeds and fails together, fostering a culture of trust, continuous improvement, and shared accountability where every individual's contribution drives our collective success.   Key Responsibilities • Own assigned advanced packaging layer(s), ensuring all POR defect inspection, classification, and review operations are properly established with healthy inspection recipes and NPI procedures defined. • Drive ADC implementation to ensure accurate defect classifications and maintain defect classification specs and Defect Menagerie for all assigned layers. • Partner with metro tool owners to set up and maintain SPC charts for every defect mode and layer, create OCAPs for Metro MTs and module engineering to respond to OOC events and defect tracers. • Own process health and product quality for the WPM manufacturing line, including defect performance, yield trends, excursions, and baseline process changes. • Own defect excursions through resolution, including containment, wafer/lot risk assessment, disposition, root cause, downstream impact, quality events, and non-POR material. •  Drive systematic defect reduction and process improvement using process/metrology data, SORT data, DOEs, FRECLs, ATVs, and experiments with process modules. • Co-lead cross-functional defect health reviews, including IMTs, Focus Teams, and Task Forces covering tracers, trends, OOCs, wafers-at-risk, excursions, and corrective actions. •  Extract, analyze, and correlate data to improve defects, yields, and VF matching, identifying key toolsets driving defects through analysis, MBPS, and FA. • Quantify chronic defect gaps to goal, document roadmaps to close gaps, and ensure defect health dashboards are operational and incorporated into factory business processes. • Communicate defect metrics and findings to module and factory stakeholders through weekly summaries and strategic quarterly reviews, while providing defect training to technicians, peers, and module teams.   Behavioral traits: • Proven ability to lead problem-solving initiatives and process improvement projects. • Exceptional communication skills for effectively collaborating across multidisciplinary teams. • Passion for mentoring and fostering technical growth within teams. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates.  This position is not eligible for Intel immigration sponsorship   Minimum Qualifications   • Bachelor's degree in engineering or a related field and 3+ years of experience OR Master's degree in enginee