Director Post-Si Electrical Validation Engineering

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking a Director of Post-Si Electrical Validation Engineering to lead the development, bring-up, and validation of ASIC SerDes and PCIe PHY products that enable rack-scale AI infrastructure. Working closely with ASIC, systems, firmware, signal integrity, power integrity, mechanical, thermal, manufacturing, and customer engineering teams, you will guide products from concept and architecture through qualification and mass production. This is a hands-on leadership role in a fast-moving environment. You will lead a talented engineering team while stepping in to solve complex technical problems, engage directly with customers, and improve hardware development processes. Your work will help ensure Astera Labs’ connectivity and memory products deliver reliable, high-performance systems for cloud service providers, server manufacturers, and networking OEMs. Key Responsibilities • Board Product Strategy and Technical Leadership • • Lead ASIC Electrical-level (PHY) validation strategy across product definition, architecture, PCB/test fixture development, Validation Automation, data review, bring-up, debug, optimization, qualification, and production release. • • Define validation plans, coverage goals, risk assessments, schedules, and exit criteria for high-speed ASIC and PHY IP • • Make hands-on technical contributions to unblock critical design, validation, and customer issues in a dynamic, fast-paced environment. • High-Speed SerDes Validation • • Direct ASIC Power-On and bring-up, silicon/PCB debug, PVT characterization, margin analysis, and performance optimization across voltage, temperature, channel, and workload conditions. • • Validate high-speed NRZ and PAM4 SerDes-based protocols, including PCIe Gen 3 and above • • Apply signal/power integrity, SerDes/PHY knowledge, coding, and lab expertise to identify risks and drive practical solutions across circuits, power distribution, connectors, sockets, and cables. • Cross-Functional and Customer Execution • • Partner with ASIC, system validation, firmware, systems, mechanical, thermal, quality, compliance, manufacturing, and customer engineering teams to deliver robust products. • • Engage key internal customers to understand system requirements, evaluate form factors, propose complete board solutions, and resolve issues through production support. • • Collaborate with external vendors for test equipment, bench sockets, temperature forcing units, RF cables, PCB vendors, and related suppliers to ensure validation platforms are automated, robust, and scalable. • Team Development and Productization • • Build, mentor, and develop a high-performing engineering team while establishing clear ownership, technical standards, and execution mechanisms. • • Drive products from concept to mass production, including validation data reviews, code/automatin reviews, validation reporting, documentation, and post-production support. • • Improve post-Silicon development processes and methodol