Jobs / United States / Boeing Company
ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal)
Boeing Company · 🇺🇸 USA - Albuquerque, NM
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 72 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 7 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Boeing Company paid sponsored hires in similar roles11 certified filings for “Mechanical System Design & Analysis Engineer” (Mechanical Engineers) in WA: $135k–$170k, median $143k. Most were filed at wage level IV (100%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Boeing Company
The US Department of Labor certified 72 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 7 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Boeing Company →
About the role
ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal) Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/FPGA Design or Verification Engineers (Lead, Senior, or Principal) to join us as part of our Boeing Electronic Products team at the heart of Boeing’s products; ASICs and FPGAs in Albuquerque, NM. From complex digitally beamformed phased arrays for constellation satellite programs to computing and networking equipment for commercial airplanes, the Boeing Electronic Products group develops ASICs and FPGAs that are at the heart of Boeing’s products. We leverage leading-edge technology and work with world-class partners to provide some of the most complex SoCs in the world. We develop robust, high-performance custom processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. And we're applying the latest digital IC design processes with industry-best tools to enable applications that cut across every domain at Boeing. Our diverse development portfolio provides opportunities to learn with exposure to the breadth of the Boeing product line – approximately half our design work is within the Space & Launch business unit, and half is from other parts of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC/FPGA Engineer on the Boeing Electronic Products team you will develop state-of-the-art digital ICs/SoCs to support the most critical programs across the enterprise. This is a unique time where we’re hiring design and verification engineers at every level as we’re only limited by our bandwidth for new projects. We collaborate with other electronics groups across the company and around the world and support ASIC/FPGA design and verification for electronics that we build in El Segundo or for units designed at other sites. Within the LEOS team, you will be working with high-performance laser gimbal control systems. Responsibilities encompass the design and development of FPGA designs and their embedded software. You’ll work with cross-functional teams, including hardware and software engineers, to define/refine system requirements, specifications, and ensure seamless software-hardware compatibility. Specific responsibilities include: - Conduct unit-level testing, verification, and validation of embedded software and firmware, utilizing debugging tools like oscilloscopes and logic analyzers to identify and resolve issues. - Create and maintain technical documentation, including requirements documents, design specifications, test plans, and interface control documents. - Support the integration of software and hardware components, from initial hardware bring-up to final system validation. - Analyze and enhance the efficiency, stability, scalability, and performance of system resources, often within the constraints of low power or memory. Position Responsibilities: • Lead FPGA/ASIC designs, including multi-FPGA/ASIC programs and teams with design and verification engineers, and manage team execution to meet program milestones • Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs • Explore trade-space of potential ASIC/FPGA technologies and determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance • Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) • Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed •