ASIC / FPGA Design Verification Engineer - (Associate or Experienced)

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About the role

ASIC / FPGA Design Verification Engineer - (Associate or Experienced) Company: Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design Verification Engineers to join us as part of our Boeing Electronic Products team at the heart of Boeing’s products in El Segundo or Huntington Beach, CA. Mission Develop adaptable verification engineers who build strong technical fundamentals, become independent owners of assigned scope, and grow from guided execution toward ownership of verification work of moderate complexity. Level Intent • Level II – Learn department processes, communicate proactively, build independence, and manage assigned verification scope. • Level III – Independently own verification scope of moderate complexity and support closure, integration, and traceability activities. Overview Engineers support ASIC, FPGA, and SoC verification activities across advanced aerospace programs including space systems, satellite technologies, NASA mission support, aviation platforms, communications systems, and related digital subsystems while gaining exposure to broader digital product development activities. Candidates are expected to possess strong verification fundamentals including simulation concepts, debug methods, coverage approaches, requirements traceability awareness, and general digital verification methodology concepts. Experience with UVM is strongly preferred, and engineers should be prepared to discuss verification fundamentals, SystemVerilog usage, coverage strategy, reusable verification concepts, and their current level of UVM understanding during interviews. Behavioral Expectations Engineers are expected to communicate status, blockers, assumptions, risks, and learning needs proactively while developing increasing ownership. The role emphasizes growth toward independent execution and effective management of personal scope of work. Teams combine engineers with complementary technical strengths. Engineers are encouraged to build deeper expertise in selected areas while collaborating across broader verification activities to support overall program goals. Responsibilities • Execute assigned verification tasks and progressively increase ownership. • Develop simulation, debug, coverage, and requirements traceability skills. • Contribute to SystemVerilog and UVM environments, tests, UVCs, and reusable infrastructure. • Support integration investigations and system-level debug activities. • Contribute to verification objectives, coverage assessments, and closure activities appropriate to experience level. • Own verification scope of moderate complexity at Level III. Engineers initially support assigned verification activities while developing increasing ownership, stronger technical depth, and broader understanding of the verification lifecycle. The role emphasizes growth from guided execution toward independent management of verification scope. Engineers contribute to simulation, debug, coverage assessment, requirements traceability activities, integration support, and closure efforts appropriate to experience level. Candidates are expected to build proficiency in SystemVerilog, UVM environments, reusable verification infrastructure, UVC development, and broader verification methodologies over time. Level III engineers are expected to independently own verification scope of moderate complexity, communicate risks and dependencies proactively, support integration investigations and system-level debug activities, and contribute to verification objectives and closure activities while continuing to broaden technical capability. This position is expected to be 100% onsite.  The selected candidate will be required to work onsite at one of the listed locations

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