Senior System Integration and Feature Validation Engineer

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About the role

NVIDIA pioneered graphics and is now the global AI leader, delivering breakthrough performance and efficiency across every important industry. As an NVIDIAN, you will tackle problems that lie between architecture, silicon, firmware, software, and production. Your judgment in ambiguous, cross-team feature integration determines whether a program ships on schedule. NVIDIA’s Silicon Co-Design Group is looking for a flexible hardware engineer to join its System Features and System Integration teams. Our responsibilities cover everything from architecture to bring-up and release. We focus on feature integration, debugging, validation, and productization for all NVIDIA GPU, CPU, Client and SoC products. Small decisions in feature integration significantly affect boot, clocks, DVFS, system controllers, pstates, circuits, and all areas where hardware and software meet. This role is not about checklist compliance or feature sign-off. Instead, it is where multi-team feature failures are either root-caused and resolved or cause program delays. The two most critical challenges in this position are: What you will be doing : • End to End responsibility for the integration and product development of system features across — boot, clocks, DVFS, performance and power system controllers, and certain circuits. • Lead debugging and root-cause resolution on the most challenging cross-stack feature issues covering silicon, firmware, driver, and platform — delivering productized fixes and reusable workarounds. • Build and deploy AI-enabled workflows for feature validation, debug, and triage — with explicit guardrails and measurable impact on cycle time, coverage, or escape rate. • Support silicon bring-up, feature deployment, and GPU/SoC qualification through feature checks, PVT stress and stability testing, and lab debug. • Build the tools, scripts, and infrastructure the team relies on — and improve validation and productization processes for greater quality and efficiency. • Partner with globally distributed teams — architecture, ASIC, firmware, driver, software, and multiple bring-up teams. What we need to see : • BTech / BE or MTech / ME in Electronics, Electrical, or Computer Engineering along with over 5 years of experience in post-silicon bring-up, system integration, or feature design and validation for released GPU, CPU, or SoC products. At least once, you should have diagnosed a vague, cross-team feature failure and delivered a finalized fix. • Strong end-to-end understanding of hardware, firmware, and software interaction — with fundamentals in board and system development, DVFS, control loops, SI/PI, timing, clocking, high-speed I/O, PVT, and thermal — and hands-on silicon, board, and lab-debug muscle memory. • Practical understanding of GPU, CPU, or SoC architectures within at least one of PC, datacenter, or automotive environments — proven experience leading efforts to address unclear issues spanning multiple teams. • Proven validation approach using smart AI technology you designed or scaled, not only used — with adoption beyond yourself and measurable impact on debug velocity, coverage, or escape rate. You can detail the limits you set and where smart AI tools may introduce hazards in your workflow. Ways to stand out from the crowd: • A history of building reusable feature-integration methodology, debug playbooks, or validation frameworks that other programs or teams adopted. These are backed by patents, conference papers, or talks where you were encouraged to present. • Practical subsystem expertise in DVFS, boot / clock / reset, power management controllers, high-speed I/O, or thermal — including failure modes, debug instrumentation, and the compromises encountered during production. • Experience partnering deeply wit

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