Jobs / United States / Intel Corporation
Quantum Packaging Signal/Power Integrity (SI/PI) Engineer
Intel Corporation · 🇺🇸 US, Oregon, Hillsboro
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Intel Corporation paid sponsored hires in similar roles45 certified filings for “Packaging Engineer” (Electronics Engineers, Except Computer) in AZ: $115k–$143k, median $139k. Most were filed at wage level III (59%) — 3 lottery entries, ≈46% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Intel Corporation
The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Intel Corporation →
About the role
Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Signal/Power Integrity (SI/PI) Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Modeling and simulation of packaging hardware including redistribution layers (e.g., interposers, RDLs), IC substrates, and silicon testchip routing - Work closely with stakeholders to meet design requirements - requirements come from both theory and hardware teams. In some pathfinding projects, you will be asked to participate in creating requirements and novel packaging hardware. - System-level modelling and simulation; end-to-end simulations to ensure designs meet system-level requirements - Deliver and disseminate design milestones to stakeholders - Communicate designs in presentations and relevant documentation - Stay current with the latest developments in packaging technology and design techniques by attending conferences and reading papers As a successful candidate, you must possess - Excellent communication and presentation skills for technical and non-technical audiences - Strong analytical thinking and problem-solving capabilities - Collaborative mindset with ability to work effectively across diverse teams - Adaptability to work in a fast-paced, innovative research environment - Passion for pushing the boundaries of quantum technology development Join Intel's Quantum Computing Group where we are building the future of quantum computing. If you're passionate about working at the forefront of quantum computing packaging and want to work with the resources and expertise of the world's leading semiconductor company, we want to hear from you. Apply today and discover your place in our world-changing work. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of relevant industry job experience, internship experience and/or schoolwork/classes/research. Minimum Qualifications: M.S. degree in Electrical Engineering, Physics or related field AND 3+ years of experience in SI/PI for packaging, silicon testchip, or other related hardware. OR Ph.D. degree in Electrical Engineering, Physics or related field with academic or work experience in the related areas. The experience must include: - SI/PI modeling, simulation, and optimization with simulation software such as SIwave, HFSS, ADS, and related. - SI/PI/thermal impact on IC substrate design choices. - Design experience with large form factor IC substrates. Preferred Qualifications: - 1+ years of experience with testchip