Jobs / United States / Intel Corporation
Quantum Qubit Design Engineer
Intel Corporation · 🇺🇸 8 Locations
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Intel Corporation paid sponsored hires in similar roles211 certified filings for “Component Design Engineer” (Electronics Engineers, Except Computer) in CA: $125k–$167k, median $142k. Most were filed at wage level III (43%) — 3 lottery entries, ≈46% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
Or apply yourself on the official page →
Sponsor Radar — Intel Corporation
The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Intel Corporation →
About the role
Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans the entire quantum compute stack while harnessing the power of Intel's 18A process and design infrastructure. We are seeking an exceptional Quantum Design Engineer to join our pioneering quantum computing team. In this position, you will be joining a team of incredibly talented engineers focused on the challenging task of scaling our quantum computing chips to millions of qubits. Here you will be involved in all aspects of the qubit chip process from initial conception through Process-Design-Kit definition, design execution and tapeout, along with ensuring silicon runs smoothly in fab and final system integration. You'll work closely not only with our qubit, control, system integration, and software/algorithms teams, but also with teams in Foundry lithography, process and design. You'll be working at the intersection of cutting-edge semiconductor technology and quantum physics, creating solutions that push the boundaries of what's possible in computing. Ready to help build the future of quantum computing? Apply now and be part of this extraordinary journey Key Responsibilities • Work alongside lithography, process integration, measurement, and PDK engineers to establish qubit processes and design rules • Architect qubit and readout element standard cell design and automation • Engage with TCAD and PDK engineers and design tool vendors to create qubit and read-out universal process files and qubit level models and extraction capability • Partnering with quantum software and control engineers to analyze tradeoffs on quantum error correction schemes vs qubit topology • Design automation to enable front end design automation and routing generation for enabling routing of large scale quantum processors • Creation of Automated Place and Route flows to enable qubit routing, including AI and machine-based learning routing optimization for large I/O counts • Working with PDK engineers and design tool vendors to create new customized EDA tool capability to enable routing of large-scale quantum processors • Drive signal integrity analysis to define routing strategies for large scale qubit processors and work to define and release customized PDKs • Perform signal integrity analysis and optimization for qubit processors to ensure optimal performance for signal integrity and crosstalk • Working with PDK engineers and design tool vendors to create new signal extraction capability for large scale quantum processors • Work in a collaborative team to execute design of qubit processors from PDK implementation through Tapeout and Fab NPI • Perform industry standard design validations such as DRC, LVS, and Extraction prior to tapein signoff • Work closely with Control, Packaging and System teams to co-design Interposer interfaces and routing strategies for bridging the Qubit processor to ASIC control • Designing and taping out electrical characterization test structures to characterize qubit and interconnect performance and yield • Working with PDK engineers and design tool vendors to create new customized EDA tool capability to enable thermal analysis of large scale quantum processors • Implement PDK collateral into customized design environments and