Jobs / United States / Intel Corporation
Semiconductor Packaging Integration Research Manager
Intel Corporation · 🇺🇸 2 Locations
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Intel Corporation paid sponsored hires in similar roles76 certified filings for “Engineering Manager” (Architectural and Engineering Managers) in CA: $193k–$221k, median $214k. Most were filed at wage level III (36%) — 3 lottery entries, ≈46% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Intel Corporation
The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Intel Corporation →
About the role
Job Details: Job Description: About the Team Foundry Technology Research is responsible for developing the breakthrough technologies that will power future generations of semiconductor manufacturing. The team conducts advanced research in devices, materials, interconnects, patterning, packaging, heterogeneous integration, and system technologies, while partnering closely with technology development, manufacturing, and external research ecosystems. Researchers help translate pioneering concepts into viable semiconductor solutions that influence Intel Foundry's long-term roadmap and future customer offerings. About the Role The Semiconductor Packaging Integration Research Manager is responsible for leading advanced packaging integration research to enable next-generation heterogeneous semiconductor technology and systems. This role defines and drives early-stage integration strategies across package architecture, chiplet assembly, substrate/interposer technology, wafer-level and die-level integration reliability, and manufacturability. The manager guides exploratory concepts from research to pathfinding through feasibility demonstration, prototype learning, technology readiness assessment, and transfer to development or manufacturing teams, while partnering closely with device, design, process, materials, reliability, modeling, test, manufacturing, university, supplier, and foundry ecosystem partners. Key Responsibilities: • Lead packaging integration research programs focused on heterogeneous integration, chiplets, 2.5D/3DIC, hybrid bonding, wafer-level packaging, and emerging die-to-die interconnect technologies. • Define integration research strategy, technical roadmaps, research milestones, and decision criteria aligned to future product, platform, and system-level scaling requirements. • Manage multidisciplinary team of integration researchers, packaging technologists, process integration engineers, modeling experts, design, and technical program leads. • Translate system requirements into package integration solutions by balancing performance, power, area, latency, bandwidth, thermal behavior, mechanical stress, reliability, cost, and manufacturability. • Partner with silicon design, device, process, substrate, assembly, test, reliability, thermal, signal integrity, power delivery, failure analysis, and manufacturing teams to close cross-domain integration gaps. • Drive feasibility studies, architecture trade-off analysis, process module evaluation, design rule development, prototyping, design-of-experiments, and experimental validation for new integration concepts. • Lead technology readiness assessments, integration risk reviews, failure analysis learning cycles, reliability evaluations, and manufacturing feasibility reviews for early-stage packaging options. • Drive intellectual property, technical publications, competitive benchmarking, and internal knowledge transfer related to advanced packaging integration. • Guide research-to-development transfer by defining integration requirements, qualification gaps, process control needs, manufacturability risks, cost implications, and scaling paths. • Communicate technical progress, trade-offs, risks, investment needs, and strategic recommendations to senior technical and business leaders. Key Competencies • Si-Package co-optimization across process, integration, electrical, thermal, mechanical, reliability, manufacturability, and cost dimensions • Advanced packaging integration research leadership and technical vision • Heterogeneous integration, chiplet, 2.5D/3DIC, hybrid bonding, and emerging interconnect expertise • Technology pathfinding, roadmap definition, research portfolio management, and research-to-development transfer • Modeling, simulation, prototyp