ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) – (Experienced, Lead, or Senior)

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ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) – (Experienced, Lead, or Senior) Company: The Boeing Company Boeing Defense, Space and Security is hiring ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) at various levels of experience to join the team in Mountain View, CA. Boeing Space, Intelligence & Weapons Systems organization is seeking multiple ASIC engineers across experience levels to advance mission‑critical digital subsystems. Candidates may focus on Design‑for‑Test (DFT) / ASIC backend test infrastructure, or on Physical Design (synthesis and static timing analysis) responsibilities. You will work on leading‑edge ASICs used in space and aerospace systems—driving architecture, verification, tapeout readiness, silicon debug, and cross‑discipline integration with architecture, RTL, verification, DFT, and external backend partners. Position Responsibilities: • Design and implement DFT architectures and test access mechanisms: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, memory BIST, and scan compression. • Develop and validate TAP/JTAG and IJTAG infrastructures; produce BSDL/ICL/PDL artifacts; support ATPG pattern generation and coverage optimization. • Drive pattern generation, memory test validation, at‑speed test, silicon debug (scan, at‑speed, bring‑up), and post‑silicon validation. • Perform synthesis, equivalence checking, static timing analysis (STA), constraints generation/management, timing convergence and ECO implementation at block and chip level. • Support clean netlist handoffs and predictable convergence by partnering with RTL, verification, DFT, backend partners, and vendors. • Support chip‑level integration, top‑level timing closure, signoff readiness, and tapeout activities. • Contribute to methodology development, automation, tool evaluations, flow documentation, and deployment of best practices for next‑generation products. • Troubleshoot complex cross‑domain timing and CDC issues; propose and implement robust, repeatable fixes. • Coordinate with external partners/customers on custom DFT interfaces, security, and backend flows as applicable. • Mentor engineers and lead technical efforts (for senior/lead levels). • Occasional travel and after‑hours meetings during critical milestones. How to make your application stand out : Please include a cover letter or brief summary of relevant DFT or ASIC physical design experience and specific examples of impact (e.g., achieved timing closure on X‑nm blocks, implemented MBIST with Y% coverage, reduced ATPG time by Z%, led ECOs to tapeout). This position is expected to be 100% onsite.  The selected candidate will be required to work onsite at the listed location. Basic Qualifications (Required Skills/Experience): • This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required. • Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement • 5+ years of ASIC/FPGA design for test or physical design experience • Proficiency in scripting for automation and analysis (Tcl, Python, Perl). Preferred Qualifications (Desired Skills/Experience): • Lead, Level 4: 9+ years related engineering experience and demonstrated technical leadership. • Senior, Level 5: 14+ years related engineering experience and demonstrated technical leadership. • Strong analytical, problem‑solving, and communication skills • Bachelor’s or Master’s Degree in E

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