Jobs / United States / Intel Corporation
AI Software Technical Intern
Intel Corporation · 🇺🇸 US, California, Santa Clara
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Intel Corporation paid sponsored hires in similar roles139 certified filings for “Software Engineer” (Software Developers) in CA: $144k–$178k, median $156k. Most were filed at wage level III (52%) — 3 lottery entries, ≈46% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Intel Corporation
The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Intel Corporation →
About the role
Job Details: Job Description: Role Overview We are seeking a driven and curious Technical Intern to join our AI Software and Hardware Architecture team. In this role, you will work at the intersection of next-generation GPU architecture, performance simulation, and modern AI engineering. Our team develops architectural models and virtual platforms (VPs) to project, evaluate, and optimize the performance of future high-performance computing (HPC) and AI GPU architectures before silicon is taped out. As part of this mission, you will actively integrate the latest generative AI capabilities-including GitHub Copilot, custom Large Language Model (LLM) agents, and developer tooling integrations-directly into our architectural modeling, automated testing, and performance analysis pipelines. This internship offers an opportunity to gain hands-on experience with production-scale architectural simulators while pioneering modern, AI-augmented hardware engineering practices. Key Responsibilities Virtual Platform Development and Architecture Simulation • Collaborate with senior architects to develop, calibrate, and validate cycle-approximate or cycle-accurate Virtual Platform (VP) models for future GPU architectures (compute engines, memory fabric, cache hierarchies, and interconnects). • Implement functional and performance simulation components in modern C++ and SystemC/TLM frameworks. • Assist in porting, configuring, and executing graphics and compute workloads (e.g., PyTorch, SYCL, OpenCL, Vulkan/DirectX) across simulated environments. AI-Augmented Workflow Integration and Automation • Accelerate development and debugging efficiency by leveraging GitHub Copilot and state-of-the-art LLM capabilities across team repositories. • Prototype and deploy agentic AI workflows and tools (e.g., Model Context Protocol [MCP] integrations, automated log and trace summarization, error diagnosis). • Build AI-assisted test generation tools and validation scripts using Python and unit testing frameworks (e.g., GoogleTest). Performance Analysis and Telemetry • Collect, profile, and analyze trace-driven simulation data to pinpoint memory subsystem bottlenecks, cache miss penalties, and pipeline stalls. • Create automated visualization dashboards and reporting scripts to present performance trade-offs to senior architecture and design teams. • Investigate anomaly detection in large-scale simulation telemetry using machine learning and statistical analysis techniques. Qualifications: Minimum Qualifications • Currently enrolled in an accredited Master's or Ph.D. program in Computer Science, Computer Engineering, Electrical Engineering, or a closely related discipline. • Strong proficiency in C++ (modern C++17/20 preferred) and Python. • Solid foundational knowledge of computer architecture principles (cache hierarchies, memory coherence, pipelining, and vector/SIMD processing). • Experience with Linux/Unix environments, version control systems (Git), and modern build pipelines (CMake, Ninja). • Familiarity with utilizing AI developer tooling (e.g., GitHub Copilot, Anthropic APIs, or local LLM runtimes) for software engineering. Preferred Qualifications Prior coursework or project experience in: • GPU architecture, parallel programming, or accelerated computing (CUDA, SYCL, OpenCL, or GPU compute APIs). • Virtual Platforms, architectural simulators (e.g., gem5, SystemC/TLM, or proprietary simulator platforms). • Software testing and test-driven development (TDD) using frameworks like GoogleTest (gtest). • Experience building LLM-assisted developer agents, prompt engineering pipelines, or custom developer automation tooling. • Familiarity with hardware/software co-design concepts and performance modeling methodologies. What we offer