Jobs / United States / ionq
Senior QPU Design Engineer
ionq · 🇺🇸 Oxford
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- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
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Sponsor Radar — ionq
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About the role
About IonQ: IonQ, Inc . [NYSE: IONQ] is the world’s leading quantum platform and merchant supplier - delivering integrated quantum solutions across computing, networking, sensing, and security. IonQ’s newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting-edge systems that have been helping customers and partners including Amazon Web Services, and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense. In 2025, the company achieved 99.99% two-qubit gate fidelity, setting a world record in quantum computing performance . Headquartered in College Park, Maryland, IonQ has operations in California, Colorado, Massachusetts, Tennessee, Washington, Italy, South Korea, Sweden, Switzerland, Canada, and the United Kingdom. Our quantum computing services are available through all major cloud providers, while we also meet the needs of networking and sensing customers across land, sea, air, and space. IonQ is making quantum platforms more accessible and impactful than ever before. Location: Oxford, England, UK. Hybrid, three days per week in the Oxford office. The Role: We are looking for a Senior QPU Design Engineer to join our Processor Design team at Oxford Ionics, now part of IonQ. You will be responsible for integrating all the features required to operate our quantum computers into complex chips, contributing to the team's mission of advancing the design of high performance quantum processing units. You will work closely with scientists and fabrication engineers to bring new designs for ion trapping chips into production, and you will play an important part in shaping the hardware behind our work building the world's most advanced quantum systems. Responsibilities : In this position you will turn operational requirements into chip layout, supporting the delivery of devices that enable new technologies. You will have the opportunity to expand the range of features our chips support, contributing directly to the goal of building utility scale quantum computers. • Guiding chips through the design process, from requirements to layout and tape out • Laying out complex multi layer chips, including metal track routing and interfaces with photonics and CMOS • Collaborating with scientists to discuss their requirements and settle on specifications • Coordinating with other teams to ensure feasibility and compatibility • Taking charge of projects independently and owning delivery of the final tape out Requirements: You will need experience translating design requirements into features, alongside hands on experience in chip layout. We are looking for someone who can work across teams to discuss the many aspects of chip design, understand how different parts of a chip influence and constrain one another, take on layout work themselves, and contribute effectively within a fast moving and highly technical team. You will need to drive the design process, solve problems as they arise, and take responsibility for delivery. *]:pointer-events-auto R6Vx5W_threadScrollVars scroll-mb-[calc(var(--scroll-root-safe-area-inset-bottom,0px)+var(--thread-response-height))] scroll-mt-[calc(var(--header-height)+min(200px,max(70px,20svh)))]" data-turn-id="request-WEB:8797ed5c-8be3-4529-a392-40d56fb48ff7-0" data-turn-id-container="request-WEB:8797ed5c-8be3-4529-a392-40d56fb48ff7-0" data-testid="conversation-turn-2" data-turn="assistant"> We’re looking for someone who can guide chips through the full design process, from requirements through to layout and tape-out. You will have experience laying out complex, multi-layer chips, including metal-track routing and interfaces with photonics and CMOS. You’ll collabo