Jobs / United States / Intel Corporation
SoC Analog & Mixed-Signal Design Engineer
Intel Corporation · 🇺🇸 US, Oregon, Hillsboro
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Intel Corporation paid sponsored hires in similar roles11 certified filings for “SoC Design Engineer” (Architectural and Engineering Managers) in TX: $160k–$224k, median $192k. Most were filed at wage level II (36%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Intel Corporation
The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Intel Corporation →
About the role
Job Details: Job Description: The Role and Impact Are you passionate about solving complex analog and mixed-signal design challenges and developing technology that powers the next generation of computing? As a SoC Analog & Mixed-Signal Design Engineer, you will design and optimize analog and mixed-signal circuits in advanced CMOS process technologies. You will contribute across the design lifecycle, from circuit architecture and simulation through optimization and design verification, helping deliver robust IP that meets demanding power, performance, area, timing, and yield requirements. You will collaborate with architecture, layout, and other engineering teams to solve complex circuit challenges and help deliver high-quality silicon solutions for Intel product What You’ll Do Key responsibilities will include but not limited to: • Design, develop, and build analog circuits in advanced CMOS process nodes. • Create floorplans, perform circuit design, extract chip parameters, and simulate analog behavior models. • Develop and execute test plans to verify designs against circuit and block microarchitecture specifications. • Evaluate test results, verify functionality, and optimize circuits for power, performance, area, timing, and yield goals. • Collaborate cross-functionally to report design progress and address performance or circuit design issues. • Minimize leakage, optimize power consumption, and enhance the area efficiency of analog/mixed-signal blocks. • Work closely with architecture and layout teams to ensure robust functionality and electrical capabilities. Behavioral traits that we are looking for: • Technical Problem-Solving: Applies an analytical, data-driven approach to complex and ambiguous analog circuit-design challenges. • Design Ownership: Takes ownership of assigned designs, drives technical issues toward resolution, and contributes to high-impact product outcomes. • Collaboration: Works effectively across architecture, circuit design, layout, and other cross-functional engineering teams. • Technical Communication: Clearly communicates design decisions, trade-offs, risks, results, and recommendations to technical stakeholders. • Attention to Detail: Applies disciplined engineering practices to circuit design, simulation, analysis, and verification. • Learning Agility: Continuously builds knowledge of analog circuit technologies, architectures, process technologies, tools, and design methodologies. • Innovation Mindset: Identifies opportunities to improve circuit performance, design methodologies, and engineering efficiency and applies new ideas to technical challenges. Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. • See Intel Benefits for more details. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Note: For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information Minimum Qualifications and Experience: Bachelor's degree in Electrical Engineering, Electronics, or a related field with 4+ years of experience in analog circuit design. OR a Master's degree in the same fields with 2+ years of experience. OR a PhD in the same field with 1+ of educational or work experience. Your experience describe above must be in the following: • Analog simulation tools and methodologies. • Experience with circuit optimization techniques focused on power, area, timing, and yield. • Experience with advanced process nodes and their applic