Jobs / United States / Samsung Semiconductor INC
Staff Engineer, PCIe PHY/Link Analysis
Samsung Semiconductor INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 123 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 52 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Samsung Semiconductor INC paid sponsored hires in similar roles1 certified filing for “Staff Performance Analysis Engineer” (Computer Network Architects) in MD: $150k–$150k, median $150k. Most were filed at wage level III (100%) — 3 lottery entries, ≈46% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Samsung Semiconductor INC
The US Department of Labor certified 123 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 52 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Samsung Semiconductor INC →
About the role
Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities. At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures. We are looking for a dynamic, self-motivated engineer to develop and support our cutting-edge Enterprise and Data Center SSD products. The ideal candidate will possess comprehensive expertise across the full PCIe protocol stack - from the Physical Layer (PHY) through the Data Link Layer and up to the Transaction/Transport Layer - with a proven track record in hardware/firmware design, protocol implementation, and complex link bring-up and debugging. What You’ll Do • Protocol Stack Analysis: Understand PHY/Link architecture, implementation, and integration of the PCIe protocol stack from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer, in collaboration with internal H/W teams and external vendors. • Link Bring-up & Training: Own LTSSM behavior, link training and equalization sequencing, PCIe enumeration, and configuration-space flows during device bring-up. • Transaction/Transport Layer: Analyze and validate TLP/DLLP handling, flow control, credit management, ordering rules, ACK/NAK and replay, error handling (AER), and end-to-end data integrity across the stack. • Debug & Optimization: Analyze and debug complex PHY, Link, and Transport layer issues during bring-up and sustaining stages of NVMe SSD products, from Gen1 to the latest generation (Gen7), covering protocol (LTSSM / PCIe enumeration) and PCIe feature-related issues. • Compliance & Standards: Participate in and support industry PHY/Link compliance tests, including PCI-SIG events. • Field Support: Provide onsite support for PHY/Link related tasks at customer sites and labs. • Travel: This position requires up to 25% business travel. What You Bring • BS in Computer/Electrical/Electronic Engineering or Computer Science, and 8+ years of relevant experience in hardware or a MS in Computer/Electrical/Electronic Engineering or Computer Science with 5+ years of relevant experience is required. • Protocol Expertise: Deep proficiency with the PCIe protocol spanning the entire architecture from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer. • Link Layer Mastery: Strong hands-on knowledge of LTSSM, link training/equalization, PCIe enumeration, flow control, replay/retry, and error handling (AER). • PHY Awareness: Working knowledge of PHY-layer operation (CDR to Equalizer such as VGA, CTLE, DFE, FFE, DSP, etc ) sufficient to root-cause link issues that cross the PHY/Link boundary. • Firmware & Debugging: Solid