Jobs / United States / Microchip Technology INC
Sr Tech Staff Engineer - Design (Signal & Power Integrity)
Microchip Technology INC · 🇺🇸 San Jose, CA, US
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 99 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 39 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Microchip Technology INC paid sponsored hires in similar roles2 certified filings for “Senior Engineer I - Design” (Electrical Engineers) in AZ: $81k–$99k, median $90k. Most were filed at wage level I (100%) — 1 lottery entry, ≈15% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
Or apply yourself on the official page →
Sponsor Radar — Microchip Technology INC
The US Department of Labor certified 99 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 39 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Microchip Technology INC →
About the role
Job Description: Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products. Microchip Technology Inc. has a Senior Technical Staff -Design (Signal and Power Integrity) opening based in San Jose, CA. The successful candidate will be responsible for developing and driving Signal and Power Integrity methodologies for high-speed FPGA products. You will be working with other SIPI engineers and working with a global cross functional team to provide solutions at a system level for internal and external customers. Responsibilities: • Collaborate effectively within a global team environment, demonstrating excellent communication skills (verbal and written). • Possess robust analytical and debugging capabilities for high-speed Signal Integrity and Power Integrity (SIPI) analysis across Die, Package, and Boards. • Understand channel loss mechanisms, interpret and optimize eye diagrams, and apply jitter analysis and mitigation techniques. • Demonstrate a thorough understanding of correlation methodologies and expertise in crosstalk analysis and reduction. • Possess a comprehensive grasp of Power Delivery Network (PDN) design and optimization. • Conduct extensive SIPI simulations (pre-layout and post-layout) to optimize signal integrity and power integrity performance at a system level. • Influence die changes based on simulation results to ensure optimal SIPI performance. • Implement and maintain robust SI/PI strategies throughout the product development lifecycle (die and package). • Proactively identify and address potential SIPI issues early in the design process. • Stay abreast of the latest industry trends, emerging tools, and methodologies in SIPI, PDN design, and SerDes transceiver development. • Provide technical guidance and mentorship to other SIPI engineers within the team. • Develop and refine methodologies for running simulations to ensure robust and reliable PDN systems. • Develop strategies and methodologies to guarantee robust performance of high-speed SerDes transceivers, including equalization techniques and advanced jitter analysis. • Collaborate effectively with external partners, suppliers, and customers on SI/PI-related topics. • Actively contribute to the development of new design methodologies, innovative tools, and streamlined processes to continuously improve SIPI design efficiency and product performance. Requirements/Qualifications: • Bachelor of Science (BS) degree in Electrical Engineering or Electronic --Engineering • 15+ years of relevant experience • 10+ yeas of practical, hands-on experience directly related to Signal Integrity and Power Integrity (SIPI). • Extensive practical experience in Printed Circuit Board (PCB) design and layout principles. • High-Speed SerDes (Serializer/Deserializer) experience is highly desirable, especially troubleshooting channel-related issues for 32G transceivers and beyond. • Demonstrated experience in resolving SI/PI-related challenges, including Power Delivery Network (PDN) optimization and noise mitigation. • Build and construct system level topologies for co-sims on PDN and transceivers • Expe