Jobs / United States / Astera Labs INC
AE| Principal Product Application Engineer (Scorpio)
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles26 certified filings for “Tech Lead Firmware Engineer” (Electronics Engineers, Except Computer) in CA: $157k–$216k, median $165k. Most were filed at wage level II (42%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As an Astera Labs Principal Product Application Engineer, you will need to provide technical guidance to ODMs to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. We need experience supporting the development and designing-in of semiconductor products for PCIe/CXL. There are opportunities to support key ODMs directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products. Basic Qualifications • Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, Master’s is preferred. • Minimum of 10 years’ experience designing in complex SoC/silicon products with a high speed (preferably PCIe) interface. • Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind! Required Experience • Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug. Most recent experience with PCIe 4.0 at a minimum, some experience with 5.0/CXL preferred. • Silicon/System bring-up and debug experience in customer systems. • Technical ownership of issue resolution: Driving and directing internal teams, and driving communication to customers through FAE and sales teams. • Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs. • Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences. • Global customer engagement support, with travel as required for on-site activities, reviews, and system bring-up. Preferred experience • Triaging complex customer reported issues which require taking into account multiple layers of conditions; for instance, silicon, firmware, hardware board design, and system environment. • Development/support for PCIe or Ethernet Switch or Retimer products. • PCIe compliance testing methodology and troubleshooting. • Comfort working with software/firmware associated with semiconductor products, such as; Firmware development with C-language, scripting with Python or other equivalent programming languages. • Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.