IP Design Director

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About the role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description – IP Digital Design Manager Position Overview We are seeking an experienced and highly motivated Digital Design Manager to lead the micro- architecture, design, development, and delivery of IPs and Subsystems from for next-generation switch products. This role combines deep technical expertise with strong people leadership and program management skills. The successful candidate will be responsible for managing a team of IP digital design engineers while driving the successful execution of complex IP development programs. The role requires close collaboration with Architecture, Verification, Physical Design, DFT, Firmware, Software, Product Engineering, and SoC Integration teams to ensure delivery of high-quality IPs that meet performance, power, area, quality, and schedule objectives. This position offers the opportunity to influence product roadmaps, establish engineering best practices, and contribute to the development of industry-leading semiconductor solutions. Key Roles & Responsibilities Technology Background • Deep understanding of complex networking protocols such as PCIE, UALink, Ethernet is a must • Experience of working on latest generations of these protocols is highly desirable. • Expertise of standard front-end design flows / tools / HDLs for digital design Technical Leadership • Lead the end-to-end development of digital Ips / Subsystems from architecture through silicon validation. • Partner with architects and product teams to define IP requirements, features, performance targets, and scalability needs. • Drive microarchitecture development and ensure alignment with overall SoC and product requirements. • Review and approve architecture specifications, design documents, RTL implementations, and verification plans. • Ensure IP designs achieve performance, power, area (PPA), reliability, and quality targets. • Lead technical reviews and provide guidance on complex design challenges. • Drive design trade-off decisions and risk mitigation strategies. • Lead the post-silicon support once silicon is back in the lab. Prior experience of post-silicon work is highly desirable. IP Development & Delivery • Own the successful delivery of IP/Subsystem releases according to committed schedules and quality goals. • Ensure all IP deliverables, including RTL, verification collateral, documentation, synthesis constraints, and integration guides, are completed and released on time. • Drive IP reuse strategies to maximize engineering efficiency across multiple products and platforms. • Establish standards for IP packaging, version control, configuration management, and release processes. • Ensure compliance with internal design methodologies and industry best practices for all front-end flows such as Lint, CDC, Power Analysis, Timing Constraints. • Work with cross-functional teams to ensure that requirements, dependencies from all stakeholders are met and incorporated into the deliverables Team Leadership & People Management

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