Jobs / United States / Astera Labs INC
Principal Advanced Packaging Engineer
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles26 certified filings for “Tech Lead Firmware Engineer” (Electronics Engineers, Except Computer) in CA: $157k–$216k, median $165k. Most were filed at wage level II (42%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Principal Advanced Packaging Engineer: About the Role Astera Labs is seeking a Principal Advanced Packaging Engineer to lead R&D for next-generation packaging technologies for optical chips. This is a senior individual contributor role focused on setting technical direction and driving packaging technology development for NPO and CPO products. Responsibilities • Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration. • Define and optimize wafer-level, panel-level, or die-level packaging process flows. • Drive EIC-to-PIC integration and broader optical device integration efforts. • Select and qualify packaging materials for advanced packaging. • Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development. • Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages. • Develop and maintain packaging PDKs and design rules for NPO and CPO products. Basic Qualifications: • B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field. • 8+ years of experience in semiconductor or advanced packaging engineering, with demonstrated technical leadership. • Deep expertise in advanced packaging processes, including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and overmold across wafer-, panel-, and die-level flows. • Experience with silicon photonics chip packaging and EIC/PIC integration. • Hands-on experience with advanced packaging materials, including underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants. • Proven track record of equipment and process qualification with OSAT or tool suppliers. • Experience with PDK development and packaging design rule authoring. • Strong foundation in yield analysis, reliability characterization, and process capability methodologies such as Cpk and SPC. Preferred Qualifications: • Hands-on experience with CPO or NPO product development. • Experience with optical coupling or waveguide alignment for photonic integration. • Familiarity with DFM and DFT for advanced packaging. Salary range is $205,000 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.