Jobs / United States / Astera Labs INC
Principal Digital Design Engineer
Astera Labs INC · 🇺🇸 San Jose, CA
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles14 certified filings for “Tech Lead Design Verification Engineer” (Electrical Engineers) in CA: $160k–$218k, median $206k. Most were filed at wage level IV (70%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers. Key Responsibilities • Design Ownership & Execution • Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm. • Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance • Drive designs to production, ensuring accountability for quality, schedule, and overall design success • Verification & Integration • Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues • Own third-party IP integration and block-level verification through sign-off • Work closely with post-silicon teams to facilitate silicon bring-up and debug • Technical Leadership • Mentor junior engineers to develop their technical skills and expertise • Actively contribute to the development and improvement of silicon development processes • Drive design methodology improvements and CAD automation initiatives Basic Qualifications • Bachelor's degree in Electrical Engineering or equivalent • 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets • Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis • Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation • Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar • Production experience with advanced CMOS nodes (≤7nm) • Proficiency with Cadence and/or Synopsys digital design flows Preferred Qualifications • Master's degree in Electrical Engineering or related field • Track record of delivering multiple high-performance designs to production in data-center environments • Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges • Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.) • Proven contributions to design methodology, CAD automation, or design infrastructure Salary range is $185,000 to $230,000 depending on experience, level, and business need